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this document is a general product descript ion and is subject to change without notice . sk hynix does not assume any responsibi lity for use of circuits described. no patent licenses are implied. rev 1.1 / oct. 2013 1 168ball fbga specification 8gb lpddr3 (x32)
rev 1.1 / oct. 2013 2 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) document title fbga 8gb (x32) lpddr3 revision history revision no. history draft date remark 0.1 - initial draft may. 2013 preliminary 0.2 - corrected twls and twlh in ac timing parameters jun. 2013 preliminary 0.3 - corrected a typo jun. 2013 preliminary 0.4 - added dram speed 1866mbps to ordering information jul. 2013 preliminary 1.0 final version - updated idd specification and input/output capacitance aug. 2013 1.1 - added dram speed 1866mbps oct. 2013
rev 1.1 / oct. 2013 3 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) features [ fbga ] operation temperature - (-30) o c ~ 105 o c package - 168-ball fbga - 12.0x12.0mm 2 , 0.70t, 0.50mm pitch - lead & halogen free [ lpddr3 ] ? vdd1 = 1.8v (1.7v to 1.95v) ? vdd2, vddca and vddq = 1.2v (1.14v to 1.30) ? hsul_12 interface (high speed unterminated logic 1.2v) ? double data rate architecture for command, address and data bus; - all control and address except cs_n, cke latched at both rising and falling edge of the clock - cs_n, cke latched at rising edge of the clock - two data accesses per clock cycle ? differential clock inputs (ck_t, ck_c) ? bi-directional differential data strobe (dqs_t, dqs_c) - source synchronous data transactio n aligned to bi-directional differ ential data strobe (dqs_t, dqs_c) - data outputs aligned to the edge of the data strobe (dqs_t, dqs_c) when read operation - data inputs aligned to the ce nter of the data strobe (dqs_t, dqs_c) when write operation ? dm masks write data at the both risi ng and falling edge of the data strobe ? programmable rl (read latenc y) and wl (write latency) ? programmable burst length: 8 ? auto refresh and self refresh supported ? all bank auto refresh and per bank auto refresh supported ? auto tcsr (temperature compensated self refresh) ? pasr (partial array self refresh) by bank mask and segment mask ? ds (drive strength) ? dpd (deep power down) ? zq (calibration) ? odt (on die termination)
rev 1.1 / oct. 2013 4 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) functional block diagram ck_t, ck_c zq dq0~dq31 cs0, cke0 8gb x32 device ca0 ~ ca9 dm0~dm3, vdd1, vdd2, vddca, vddq, vref(ca/dq) vss, vssca, vssq (256m x 32) note 1. total current consumption is dependent to user op erating conditions. ac and dc characteristics shown in this specification are based on a si ngle die. see the section of ?dc pa rameters and operating conditions? dqs0_t~dqs3_t, dqs0_c~dqs3_c,
rev 1.1 / oct. 2013 5 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ordering information part number memory combination operation voltage density speed package H9CKNNN8GTMPLR-NTH lpddr3 s8b 1.8v/ 1.2/1.2/1.2 8gb(x32) ddr3 1600 168ball fbga (lead & halogen free) h9cknnn8gtmplr-nuh lpddr3 s8b 1.8v/ 1.2/1.2/1.2 8gb(x32) ddr3 1866 168ball fbga (lead & halogen free) h 9 c k n n n 8 g t m p l r - n * h mcp/pop product mode : density, stack, block size voltage & i/o for nvm : voltage, i/o & option for dram : none pop lpddr3 only density, stack, ch & cs for dram : nand speed : none package material : lead & halogen free package type : generation : 1st & page buffer for nvm 1) : none 8gb, sdp 1.2v/1.2, x32, lpddr3 fbga 168 ball 12x12 temperature : mobile (-30~105?c) sk hynix memory dram speed
rev 1.1 / oct. 2013 6 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ball assignment nc nc nc nc nc nc nc nc vdd1 vssq dq30 dq29 vssq dq26 dq25 vssq dqs3_ c vdd1 vss vdd1 nc nc nc nc nc nc vss vdd2 dq31 vddq dq28 dq27 vddq dq24 dqs3_ t vddq dm3 vdd2 top view 168ball 12x12 pop x32 lpddr3 only dnu dnu dnu dnu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 dnu dnu dnu dnu vss vdd2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vss nc vdd1 zq vref (ca) vss vdd2 ca9 ca8 ca7 vddca vssca ca6 ca5 vddca ck_c ck_t vss vdd2 a b c d e f g h j k l m n p r t u v w y aa ab ac 1234567891011121314151617181920212223 cs0 nc vdd1 ca1 vssca ca3 ca4 vdd2 vss dq16 vddq dq18 dq20 vddq dq22 dqs2_ t vddq dm2 vdd2 cke0 nc vss ca0 ca2 vddca nc nc nc vssq dq17 dq19 vssq dq21 dq23 vssq dqs2_ c vdd1 vss dnu dnu dnu dnu dnu dnu dnu dnu dq15 vssq vddq dq14 dq12 dq13 dq11 vssq vddq dq10 dq8 dq9 dqs1_ t vssq vddq dqs1_ c vdd2 dm1 vref (dq) vss vdd1 dm0 dqs0_ c vssq vddq dqs0_ t dq6 dq7 dq5 vssq vddq dq4 dq2 dq3 dq1 vssq vddq dq0 a b c d e f g h j k l m n p r t u v w y aa ab ac lpddr3 commend / address lpddr3 data io power (lpddr3 : vdd1,vdd2,vddca,vref) ground (lpddr3 : vss,vssca,vssq)
rev 1.1 / oct. 2013 7 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) pin description input/output capacitance (toper; vddq = 1.14-1.3v; vddca = 1.14-1.3v; vdd1 = 1.7-1.95v, vdd2 = 1.14-1.3v) note: 1. this parameter applies to both die and package. 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147 (procedure for measur ing input capacitance using a vector ne twork analyzer (vna) with vdd1, vdd2, vddq, vss, vssca, vssq applied and all other pins floating). 3. ci applies to cs_n, cke, ca0-ca9. 4. dm loading matches dq and dqs. 5. mr3 i/o configuration ds op3-op0 = 0001b (34.3 ohm typical) 6. maximum external load capacitance on zq pin, including packaging, board, pin, resistor, and other lpddr3 devices: 5pf. symbol description type cs0 chip select input ck_c, ck_t differential clocks input cke0 clock enable input ca0 ~ ca9 command / address input dq0 ~ dq31 data i/o input/output dm0 ~ dm3 input data mask input/output dqs0_t ~ dqs3_t differential data strobe (rising edge) input/output dqs0_c ~ dqs3_c differential data strobe (falling edge) input/output zq drive strength calibration input/output vdd1 core power supply power vdd2 core power supply power vss ground ground vddq i/o power supply power vddca ca power supply power vssca ca ground ground vssq i/o ground ground vref reference voltage power parameter symbol min max unit input capacitance, ck_t and ck_c cck tbd tbd pf input capacitance, all other input-only pins ci 0.4 1.1 pf input/output capacitance, dq, dm, dqs_t, dqs_c cio 0.8 1.6 pf input/output capacitance zq czq tbd tbd pf
rev 1.1 / oct. 2013 8 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) package information 168 ball 0.5mm pitch 12 .0mm x 12.0mm fbga [t = 0.70mm max] bottom view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a b c d e f g h j k l m n p r t u v w y aa ab ac 0.500 x 22 = 11.000 12.000 0.100 0.500 12.000 0.100 0.500 x 22 = 11.000 0.500 0.100 168 x ? 0.3300.050 (post reflow ? 0.3400.050) 0.2700.050 0.630 + 0.070 - 0.100 seating plane c front view ?0.15 m c ab a1 index mark 0.10 c
rev 1.1 / oct. 2013 9 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) 8gb lpddr3 sdram
rev 1.1 / oct. 2013 10 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) input/output functional description symbol type description ck_t, ck_c input clock: ck_t and ck_c are differential clock inpu ts. all double data rate (ddr) ca inputs are sampled on both positive and negative e dge of ck_t. single data rate (sdr) inputs, cs_n and cke, are sampled at the positive clock edge. clock is defined as the differential pair, ck_t and ck_c. the positive clock edge is defined by the crosspoint of a rising ck_t and a falling ck_c. the negative clock edge is defined by the crosspoint of a falling ck_t and a rising ck_c. cke input clock enable: cke high activates and cke low deactivates internal clock signals and therefore device input buffers and output drivers. power savings modes are entered and exited through cke transitions. cke is considered part of the command code. cke is sampled at the positive clock edge. cs_n input chip select: cs_n is considered part of the command code.cs_n is sampled at the posi- tive clock edge. ca0 - ca9 input ddr command/address inputs: uni-directional command/address bus inputs. ca is considered part of the command code. dq0 - dq15 (x16) dq0 - dq31 (x32) i/o data input/output: bi-directional data bus dqs0_t, dqs1_t, dqs0_c, dqs1_c (x16) dqs0_t - dqs3_t, dqs0_c - dqs3_c (x32) i/o data strobe (bi-directional, differential): the data strobe is bi-directional (used for read and write data) and differential (dqs_t an d dqs_c). it is output with read data and input with write data. dqs_t is edge-aligned to read data and centered with write data. for x16, dqs0_t and dqs0_c correspond to the data on dq0 - dq7; dqs1_t and dqs1_c to the data on dq8 - dq15. for x32 dqs0_t and dqs0_c correspond to th e data on dq0 - dq7, dqs1_t and dqs1_c to the data on dq8 - dq15, dqs2_t and dqs2_c to the data on dq16 - dq23, dqs3_t and dqs3_c to the data on dq24 - dq31. dm0-dm1 (x16) dm0-dm3 (x32) input input data mask: dm is the input mask signal for writ e data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs_t. althou gh dm is for input only, the dm loading shall match the dq and dqs_t (or dqs_c). for x16 and x32 devices, dm0 is the input data mask signal for the data on dq0-7. dm1 is the input data mask signal for the data on dq8-15. for x32 devices, dm2 is the input data mask si gnal for the data on dq16-23 and dm3 is the input data mask signal for the data on dq24-31. odt input on-die termination: this signal enables and disables termination on the dram dq bus according to the specified mode register settings. vdd1 supply core power supply 1 vdd2 supply core power supply 2 vddca supply input receiver power supply : power for ca0-9, cke, cs_n, ck_t and ck_c input buf- fers. vddq supply i/o power supply : power supply for data input/output buffers. vrefca supply reference voltage for ca command and control input receiver : reference voltage for all ca0-9, cke, cs_n, ck_t and ck_c input buffers. vrefdq supply reference voltage for dq input receiver : reference voltage for all data input buffers. vss supply ground vssca supply ground for input receivers vssq supply i/o ground : ground for data in put/output buffers zq i/o reference pin for output drive strength calibration
rev 1.1 / oct. 2013 11 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) functional description lpddr3-sdram is a high-speed synchronous dram device internally configured as an 8-bank memory. these devices contain the fo llowing number of bits: 4 gb has 4,294,967,296 bits 8 gb has 8,589,934,592 bits 16 gb has 17,179,869,184 bits 32 gb has 34,359,738,368 bits lpddr3 devices use a double data rate architecture on the command/address (ca) bus to reduce the number of input pins in the system. the 10-bit ca bus contains command, address, and bank information. each command uses one clock cycle, during which command information is transferred on both the positive and ne gative edge of the clock. these devices also use a double data rate architecture on the dq pins to achiev e high speed operation. the double data rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per dq every clock cycle at the i/o pins. a single read or write ac cess for the lpddr3 sdram effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal dram core and eight corresponding n-bit wide, one-half-clock- cycle data transfers at the i/o pins. read and write accesses to the lpddr3 sdrams are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence . accesses begin with the registration of an activate command, which is then followed by a read or write command. the address and ba bits regi stered coincident with the activate command are used to select the row and the bank to be accessed. the a ddress bits registered coincident with the read or write command are used to select the bank and the starting column loca tion for the burst access. prior to normal operation, the lpddr3 sdram must be initialized. the following section provides detailed information covering device initialization, register defini tion, command description and device operation. lpddr3 sdram addressing note: 1. the least-significant column address c0, c1 is not tr ansmitted on the ca bus, an d is implied to be zero. 2. trefi values for all bank refresh is tc = -30 ~ 85 c, tc means operating case temperature. 3. row and column address values on the ca bus which are not used are ?don?t care?. density 4gb 8gb 16gb number of banks 888 bank addresses ba0 - ba2 ba0 - ba2 ba0 - ba2 t refi (us) 3.9 3.9 3.9 x16 row addresses r0 - r13 r0 - r14 r0 - r14 column addresses c0 - c10 c0 - c10 c0 - c11 x32 row addresses r0 - r13 r0 - r14 r0 - r14 column addresses c0 - c9 c0 - c9 c0 - c10
rev 1.1 / oct. 2013 12 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) state diagram self idle 1 writing precharging power writing act rd sref ref pd mrw pdx pdx pd wr automatic sequence command sequence rda wra pr, pra refreshing refreshing down power down active *1 with reading with active idle reading writing pr(a) = precharge (all) mrw = mode register write sref = enter self refresh ref = refresh pd = enter power down pdx = exit power down act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) srefx rd mr autoprecharge autoprecharge deep power dpdx power down on write mrr = mode register read srefx = exit self refresh dpd = enter deep power down dpdx = exit deep power down mrr mrr dpd power applied mr reading mr reading resetting mr reading reset reset = reset is achieved through mrw command mrr rda wra reset resetting idle active power down resetting pd pdx pr, pra
rev 1.1 / oct. 2013 13 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. in the idle state, all banks are precharged. 2. in the case of mrw to enter ca training mode or write leveling mode, the state machine will not automatically return to the idle state. in these cases an ad ditional mrw command is required to exit either operating mode and return to the idle state. see sec tions "ca training" or "write leveling". 3. terminated bursts are not al lowed. for these state transitions, the burst oper ation must be completed before the transition can occur. 4. use caution with this diagram. it is intended to provide a floorplan of the possible state transitions and commands to contr ol them, not all details. in particular, situations involving more than one bank are not captured in full detail.
rev 1.1 / oct. 2013 14 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) power-up, initialization and power-off voltage ramp and device initialization the following sequence must be used to power up the devi ce. unless specified otherwise, this procedure is mandatory. 1. voltage ramp while applying power (after ta), cke must be held low ( 0.2 vddca), and all other inputs must be between vilmin and vihmax. the device outputs remain at high-z while cke is held low. following the completion of the voltage ramp (tb), cke mu st be maintained low. dq, dm, dqs_t and dqs_c voltage levels must be between vssq and vddq during voltage ramp to avoid latchup. ck_t, ck_c, cs_n, and ca input levels must be between vssca and vddca during voltage ramp to avoid latch-up. voltage ramp power supply requirements are provided in the table ?voltage ramp conditions?. table. voltage ramp conditions note: 1. ta is the point when any power supply first reaches 300mv. 2. noted conditions apply between ta an d power-off (controlled or uncontrolled). 3. tb is the point at which all supply and referenc e voltages are within their defined operating ranges. 4. power ramp duration tinit0 (tb - ta) must not exceed 20ms. 5. the voltage difference between any of vss, vssq, and vssca pins must not exceed 100mv. beginning at tb, cke must remain low fo r at least tinit1, after which cke can be asserted high. the clock must be stable at least tinit2 prior to the first cke low-to-high tr ansition (tc). cke, cs_n, and ca inputs must observe setup and hold requirements (tis, tih) with respect to the first risi ng clock edge (as well as to subsequent falling and rising edges). if any mrr commands are issued, the clock period must be within the range defined for tckb. mrw commands can be issued at normal clock frequencies as long as all ac ti mings are met. some ac parameters (for example, tdqsck) could have relaxed timings (such as tdqsckb) before th e system is appropriately configured. while keeping cke high, nop commands must be issued for at least tinit3 (t d). the odt input signal may be in undefined state until tis before cke is registered high. when cke is registered high, the odt input signal shall be statically held at either low or high. the odt input signal remains static until the po wer up initialization sequence is finished, including the expiration of tzqinit. 2. reset command after tinit3 is satisfied, the mrw reset command must be issued (td). an optional precharge all command can be issued prior to the mrw reset command. wait at least tinit4 while keeping cke asserted and issuing nop commands. only nop commands are allowed during time tinit4. after... applicable conditions ta i s r e a c h e d vdd1 must be greater than vdd2-200mv. vdd1 and vdd2 must be greater than vddca-200mv. vdd1 and vdd2 must be greater than vddq-200mv. vref must always be less than all other supply voltages.
rev 1.1 / oct. 2013 15 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) 3. mrrs and device auto initialization (dai) polling after tinit4 is satisfied (te), only mrr commands and power-down entry/exit commands are supported. after te, cke can go low in alignment with power-down entry and exit specifications. mrr comma nds are only valid at this time if the ca bus does not need to be trained. ca training may only begin after time tf. use the mrr command to poll the dai bit and report when device auto init ialization is complete; otherwise, the co ntroller must wait a minimum of tinit5, or until the dai bit is set before proceeding. as the memory output buffers are not properly configured by te, some ac parameters must have relaxed timings before the system is appropriately configured. after the dai bit (mr0, dai) is set to zero by the memory device (dai comple te), the device is in the idle state (tf). dai status can be determined by issuing the mrr command to mr0. the device sets the dai bit no later than tinit5 after the reset command. the controller must wait at leas t tinit5 or until the dai bit is set before proceeding. 4. zq calibration if ca training is not required, the mrw initialization calibration (zq_cal) command can be issued to the memory (mr10) after time tf. if ca training is required, the ca tr aining may begin at time tf. see the section of "mode regis- ter write - ca training mode" for the ca training comman d. no other ca commands (other than reset or nop) may be issued prior to the completion of ca training. at the comp letion of ca training (tf'), the mrw initialization calibra- tion (zq_cal) command can be issued to the memory (mr10). this command is used to calibrate outp ut impedance over process, voltage, an d temperature. in systems where more than one lpddr3 device exists on the same bus, the controller must not ov erlap mrw zq_cal commands. the device is ready for normal operation after tzqinit. 5. normal operation after tzqinit (tg), mrw commands must be used to proper ly configure the memory (for example the output buffer drive strength, latencies, etc.). specifically, mr1, mr2, an d mr3 must be set to configure the memory for the target frequency and memory configuration. after the initialization sequence is co mplete, the device is ready for any vali d command. after tg, the clock frequency can be changed using the procedure de scribed in the lpddr3 specification. table. timing parameters for initialization symbol parameter value unit min max tinit0 maximum voltage ramp time - 20 ms tinit1 minimum cke low time after completion of voltage ramp 100 - ns tinit2 minimum stable clock before first cke high 5 - tck tinit3 minimum idle time after first cke assertion 200 - us tinit4 minimum idle time after reset command 1 - us tinit5 maximum duration of device auto-initialization - 10 us tzqinit zq initial calibration for lpddr3 devices 1 - us tckb clock cycle time during boot 18 100 ns
rev 1.1 / oct. 2013 16 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. power ramp and initialization sequence notes 1. high-z on the ca bus indicates nop. 2. for tinit values, see the table "t iming parameters for initialization". 3. after reset command (time te), rtt is disabled until odt function is enabled by mrw to mr11 following tg. 4. ca training is optional. initialization after reset (without power ramp) if the reset command is issued before or after the power- up initialization sequence, th e re-initialization procedure must begin at td. ck_t / ck_c supplies cke ca* dq t iscke t init0 = 20 ms (max) t init3 = 200 us (min) t init1 = 100 ns (min) t init2 = 5 t ck (min) t init4 = 1 us (min) t init5 * midlevel on ca bus means: valid nop pd reset mrr ca ta tb tc td te tf zqc t zqinit tf? odt valid t is static high or low valid tg training
rev 1.1 / oct. 2013 17 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) power-off sequence the following procedure is required to power off the device. while powering off, cke must be held low ( 0.2 vddca); all other inputs must be between vilmin and vihmax. the device outputs remain at high-z while cke is held low. dq, dm, dqs_t, and dqs_c voltage levels must be between vssq and vddq during the power-off sequence to avoid latch-up. ck_t, ck_c, cs_n, and ca input levels must be between vssca and vddca during the power-off sequence to avoid latch-up. tx is the point where any power supply drops below the minimum value specified. tz is the point where all power supplies are below 300mv. af ter tz, the device is powered off (see the table ?power supply conditions?). table. power supply conditions the voltage difference between any of vss, vs sq, and vssca pins must not exceed 100mv. uncontrolled powe r-off sequence when an uncontrolled power-off occurs, the following conditions must be met: at tx, when the power supply drops belo w the minimum values specified, all powe r supplies must be turned off and all power-supply current capacity must be at zero, exce pt for any static charge remaining in the system. after tz (the point at which all power supplies first reac h 300mv), the device must power off. the time between tx and tz must not exceed 10ms. during this period, the rela tive voltage between power supplies is uncontrolled. vdd1 and vdd2 must decrease with a slope lower than 0.5 v/ s between tx and tz. an uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device. table. power-off timing between... applicable conditions tx and tz vdd1 must be greater than vdd2?200mv vdd1 must be greater than vddca?200mv vdd1 must be greater than vddq?200mv vref must always be less than all other supply voltages symbol parameter value unit min max tpoff maximum power-off ramp time - 2 sec
rev 1.1 / oct. 2013 18 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mode register definition table below shows the mode registers for lpddr3 sdram. each register is denoted as ?r? if it can be read but not written, ?w? if it can be written but not read, and ?r/w? if it can be read and written. a mode register read command shall be used to read a mode register. a mode register write command shall be used to write a mode register. table. mode register assignment note: 1. rfu bits shall be set to `0' during mode register writes. 2. rfu bits shall be read as `0' during mode register reads. 3. all mode registers that are specified as rfu or write-only sh all return undefined data when re ad and dqs_t, dqs_c shall be t og- gled. 4. all mode registers that are specified as rfu shall not be written. 5. writes to read-only registers shall have no impacts on the functionality of the device. mr # ma <7:0> function access op7 op6 op5 op4 op3 op2 op1 op0 link 0 00h device info. r rl3 wl set b (rfu) rzqi (optional) (rfu) dai go to mr0 1 01h device feature1 w nwr (for ap) (rfu) bt bl go to mr1 2 02h device feature 2 w wr lev wl select (rfu) nwre rl & wl go to mr2 3 03h i/o config-1 w (rfu) ds go to mr3 4 04h device tempera- ture r tuf (rfu) refresh rate go to mr4 5 05h basic config-1 r manufacturer id go to mr5 6 06h basic config-2 r revision id1 go to mr6 7 07h basic config-3 r revision id2 go to mr7 8 08h basic config-4 r i/o width density type go to mr8 9 09h test mode w vendor-specific test mode go to mr9 10 0ah calibration w calibration code go to mr10 11 0bh odt w (rfu) pd ctl dq odt go to mr11 16 10h pasr_bank w pasr bank mask go to mr16 17 11h pasr_segment w pasr segment mask go to mr17 32 20h dq calibration pattern a r see the section ?dq calibration? go to mr32 40 28h dq calibration pattern b r see the section ?dq calibration? go to mr40 41 29h ca training entry for ca0-3, ca5-8 w see the section ?mode register write - ca training mode? go to mr41 42 2ah ca training exit w see the section ?mode register write - ca training mode? go to mr42 48 30h ca training entry for ca4, 9 w see the section ?mode register write - ca training mode? go to mr48 63 3fh reset w x go to mr63
rev 1.1 / oct. 2013 19 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr0 device information (ma<7:0> = 00h) note: 1. rzqi, if supported, will be set upon completion of the mrw zq initialization calibration command. 2. if zq is connected to vddca to set default calibration, op[4:3 ] shall be set to 01. if zq is not connected to vddca, either op[4:3]=01 or op[4:3]=10 might indicate a zq -pin assembly error. it is recommended that the assembly error is corrected. 3. in the case of possible assembly error (either op[4:3]=01 or op[4:3]=10 per note 4) , the lpddr3 device will default to facto ry trim settings for ron, and will ignore zq calibration commands. in either case, the system may not function as intended. 4. in the case of the zq self-test returning a value of 11b, this result indicates that the device has detected a resistor conn ection to the zq pin. however, this result cannot be used to validate the zq resistor value or that the zq resistor tolerance meets the s pecified limits (i.e. 240-ohm +/-1%). op7 op6 op5 op4 op3 op2 op1 op0 rl3 wl (set b) support (rfu) rzqi (optional) (rfu) dai dai (device auto-initialization status) read-only op0 0b: dai complete 1b: dai still in progress rzqi (built in self test for rzq information) read-only op4:op3 00b: rzq self test not supported 01b: zq-pin may connect to vddca or float 10b: zq-pin may short to gnd 11b: zq-pin self test completed, no error condi- tion detected (zq-pin may not connect to vdd or float nor short to gnd) wl (set b) support read-only op<6> 0b: dram does not support wl (set b) 1b: dram supports wl (set b) rl3 option support read-only op<7> 0b : dram does not support rl=3, nwr=3, wl=1 1b : dram supports rl=3, nwr=3, wl=1 for frequencies <=166
rev 1.1 / oct. 2013 20 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr1 device feature 1 (ma<7:0> = 01h) note: 1. programmed value in nwr register is the number of clock cycles which determines wh en to start internal precharge operation f or a write burst with ap enabled. it is determined by ru(twr/tck). table. burst sequence by bl and bt note: 1. c0 inputs are not present on ca bus. those are implied zero. 2. for bl=8, the burst address represents c2 - c0. op7 op6 op5 op4 op3 op2 op1 op0 nwr (for ap) (rfu) bt bl bl write-only op<2:0> 011b: bl8 (default) 100b: reserved all others: reserved bt write-only op<3> 0b: don?t care nwr write-only op<7:5> if nwre (in mr2 op4) = 0 001b : nwr=3 (optional) 100b : nwr=6 110b : nwr=8 111b : nwr=9 if nwre (in mr2 op4) = 1 000b : nwr=10 (default) 001b : nwr=11 010b : nwr=12 100b : nwr=14 110b : nwr=16 all others: reserved c2 c1 c0 bt bl burst cycle number and burst address sequence 1 2 3 4 5 6 7 8 0b 0b 0b seq 8 01234567 0b 1b 0b 23456701 1b 0b 0b 45670123 1b 1b 0b 67012345
rev 1.1 / oct. 2013 21 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr2 device feature 2 (ma<7:0> = 02h) note: 1. see mr0, op<7>. 2. see mr0, op<6> mr3 i/o configuratio n 1 (ma<7:0> = 03h) op7 op6 op5 op4 op3 op2 op1 op0 wr lev wl select (rfu) nwre rl & wl rl & wl write-only op<3:0> if op<6> =0 (wl set a, default) 0001b: rl = 3 / wl = 1 ( 166 mhz, optional 1 ) 0100b: rl = 6 / wl = 3 ( 400 mhz) 0110b: rl = 8 / wl = 4 ( 533 mhz) 0111b: rl = 9 / wl = 5 ( 600 mhz) 1000b: rl = 10 / wl = 6 ( 667 mhz, default) 1001b: rl = 11 / wl = 6 ( 733 mhz) 1010b: rl = 12 / wl = 6 ( 800 mhz) 1100b: rl = 14 / wl = 8 ( 933 mhz) 1110b: rl = 16 / wl = 8 ( 1066 mhz) all others: reserved if op<6> =1 (wl set b, optional 2 ) 0001b: rl = 3 / wl = 1 ( 166 mhz, optional 1 ) 0100b: rl = 6 / wl = 3 ( 400 mhz) 0110b: rl = 8 / wl = 4 ( 533 mhz) 0111b: rl = 9 / wl = 5 ( 600 mhz) 1000b: rl = 10 / wl = 8 ( 667 mhz, default) 1001b: rl = 11 / wl = 9 ( 733 mhz) 1010b: rl = 12 / wl = 9 ( 800 mhz) 1100b: rl = 14 / wl = 11 ( 933mhz) 1110b: rl = 16 / wl = 13 ( 1066mhz) all others: reserved nwre write-only op<4> 0b : enable nwr programing 9 1b : enable nwr programing > 9 (default) wl select write-only op<6> 0b : select wl set a (default) 1b : select wl set b (optional 2 ) write leveling write-only op<7> 0b : disabled (default) 1b : enabled op7 op6 op5 op4 op3 op2 op1 op0 (rfu) ds
rev 1.1 / oct. 2013 22 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. please contact us, for the supportability of the optional feature. ds write-only op<3:0> 0000b: reserved 0001b: 34.3 ?? typical pull-down/pull-up 0010b: 40 ?? typical pull-down/pull-up (default) 0011b: 48 ?? typical pull-down/pull-up 0100b: reserved for 60 ?? typical pull-down/pull-up 0110b: reserved for 80 ?? typical pull-down/pull-up 1001b: 34.3 ?? typical pull-down, 40 ?? typical pull-up (optional 1 ) 1010b: 40 ?? typical pull-down, 48 ?? typical pull-up (optional 1 ) 1011b: 34.3 ?? typical pull-down, 48 ?? typical pull-up (optional 1 ) all others: reserved
rev 1.1 / oct. 2013 23 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr4 device temperature (ma<7:0> = 04h) note: 1. a mode register read from mr4 will reset op7 to ?0?. 2. op7 is reset to ?0? at power-up. 3. if op2 equals ?1', the device temperature is greater than 85 o c. 4. op7 is set to ?1? if op2:op0 has changed at any time since the last read of mr4. 5. lpddr3 might not operate proper ly when op[2:0] = 000b or 111b. 6. for specified operating temperature range and maximum operat ing temperature refer to the section of operating temperature range. 7. lpddr3 devices shall be de-rated by adding derating values to the following core timing parameters: trcd, trc, tras, trp and trrd. tdqsck shall be de-rated according to the tdqsck de-rating in ?ac timing table?. prevailing clock frequency spec and rela ted setup and hold timings shall remain unchanged. 8. see the section of temperature sensor for inform ation on the recommended frequency of reading mr4. op7 op6 op5 op4 op3 op2 op1 op0 tuf (rfu) refresh rate refresh rate read-only op<2:0> 000b: low temperature operating limit exceeded 001b: 4 x trefi, 4 x trefipb, 4 x trefw 010b: 2 x trefi, 2 x trefipb, 2 x trefw 011b: 1 x trefi, 1 x trefipb, 1 x trefw ( ?? 85 ? c ) 100b: 1/2 x trefi, 1/2 x trefipb, 1/2 x trefw, do not de-rate ac timing 101b: 1/4 x trefi, 1/4 x trefipb, 1/4 x trefw, do not de-rate ac timing 110b: 1/4 x trefi, 1/4 x trefipb, 1/4 x trefw, de-rate ac timing 111b: high temperature operating limit exceeded temperature update flag (tuf) read-only op<7> 0b: op<2:0> value has not changed since last read of mr4 1b: op<2:0> value has changed since last read of mr4
rev 1.1 / oct. 2013 24 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr5 basic configuration1 (ma<7:0> = 05h) mr6 basic configuration2 (ma<7:0> = 06h) mr7 basic configuration3 (ma<7:0> = 07h) mr8 basic configuration4 (ma<7:0> = 08h) mr9 test mode (ma<7:0> = 09h) op7 op6 op5 op4 op3 op2 op1 op0 manufacturer id company id read-only op<7:0> 0000 0110b: hynix semiconductor op7 op6 op5 op4 op3 op2 op1 op0 revision id 1 revision id1 read-only op<7:0> 00000011b op7 op6 op5 op4 op3 op2 op1 op0 revision id 2 revision id2 read-only op<7:0> 00000000b: a-version op7 op6 op5 op4 op3 op2 op1 op0 i/o width density type type read-only op<1:0> 11b: s8 all others : reserved density read-only op<5:2> 0110b : 4gb 0111b : 8gb 1000b : 16gb all others : reserved i/o width read-only op<7:6> 00b: x32 01b: x16 all others : reserved op7 op6 op5 op4 op3 op2 op1 op0 vendor-specific test mode
rev 1.1 / oct. 2013 25 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr10 calibration (ma<7:0> = 0ah) note: 1. host processor shall not writ e mr10 with ?reserved? values 2. lpddr3 devices shall ignore calibration command when a ?reserved? value is written into mr10. 3. see ac timing table for the calibration latency. 4. if zq is connected to vssca through rzq, either the zq calibration function (see "mode register write zq calibration command ") or default calibration (through the zqreset command) is supported. if zq is connected to vddca, the device operates with defaul t calibration, and zq calibration commands are ignored. in both ca ses, the zq connection shall not change after power is applied to the device. 5. lpddr3 devices that do not support calibration shall ignore the zq calibration command. 6. optionally, the mrw zq initialization calibration command will update mr0 to indicate rzq pin connection. mr11 odt (ma<7:0> = 0bh) note: 1. rzq/4 shall be supported for lpddr3-1866 and lpddr3-2133 de vices. rzq/4 support is option al for lpddr3-1333 and lpddr3- 1600 devices. consult manufacturer specifications for rzq/4 support for lpddr3-1333 and lpddr3-1600. mr12:15 (reserved) (ma<7:0> = 0ch - 0fh) op7 op6 op5 op4 op3 op2 op1 op0 calibration code calibration code write only op<7:0> 1111 1111b: calibration command after initialization 1010 1011b: long calibration 0101 0110b: short calibration 1100 0011b: zq reset others: reserved op7 op6 op5 op4 op3 op2 op1 op0 (rfu) pd control dq odt dq odt write only op<1:0> 00b : disable (default) 01b : rzq/4 (see the note 1.) 10b : rzq/2 11b : rzq/1 power down control write only op<2> 0b : odt disabled by dram during power down 1b : odt enabled by dram during power down
rev 1.1 / oct. 2013 26 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr16 pasr bank mask (ma<7:0> = 10h) mr17 pasr segment mask (ma<7:0> = 11h) note: 1. this table indicates the ra nge of row addresses in each masked segment. x is do not care for a particular segment. op7 op6 op5 op4 op3 op2 op1 op0 bank mask bank <7:0> mask write-only op<7:0> 0b : refresh enable to the bank (=unmasked, default) 1b : refresh blocked (=masked) op bank mask lpddr3 sdram 0 xxxxxxx1 bank 0 1 xxxxxx1x bank 1 2 xxxxx1xx bank 2 3 xxxx1xxx bank 3 4 xxx1xxxx bank 4 5 xx1xxxxx bank 5 6 x1xxxxxx bank 6 7 1xxxxxxx bank 7 op7 op6 op5 op4 op3 op2 op1 op0 segment mask segment <7:0> mask write-only op<7:0> 0b : refresh enable to the segment (=unmasked, default) 1b : refresh blocked (=masked) segment op segment mask 4gb r13:11 8gb r14:12 16gb r14:12 0 0 xxxxxxx1 000b 1 1 xxxxxx1x 001b 2 2 xxxxx1xx 010b 3 3 xxxx1xxx 011b 4 4 xxx1xxxx 100b 5 5 xx1xxxxx 101b 6 6 x1xxxxxx 110b 7 7 1xxxxxxx 111b
rev 1.1 / oct. 2013 27 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mr18:31 (reserved) (ma<7:0> = 12h - 1fh) mr32 dq calibration pattern a (ma<7:0> = 20h): mrr only reads to mr32 return dq calibration patter n a. see the section of dq calibration. mr33:39 (reserved) (ma<7:0> = 21h - 27h) mr40 dq calibration pattern b (ma<7:0> = 28h): mrr only reads to mr40 return dq calibration pattern b. see the section of dq calibration. mr41 ca calibration mode entry for ca0-3, ca5-8 (ma<7:0> = 29h) see the section of ca calibration. mr42 ca calibration mode exit (ma<7:0> = 2ah) see the section of ca calibration. mr43:47 (reserved) (ma<7:0> = 2bh - 2fh) mr48 ca calibration mode entry for ca4, 9 (ma<7:0> = 30h) see the section of ca calibration. mr49:62 (reserved) (ma<7:0> = 31h - 3eh) mr63 reset (ma<7:0> = 3fh): mrw only note: for additional information on mrw reset, see mode register write command section. op7 op6 op5 op4 op3 op2 op1 op0 a4 op7 op6 op5 op4 op3 op2 op1 op0 a8 op7 op6 op5 op4 op3 op2 op1 op0 c0 op7 op6 op5 op4 op3 op2 op1 op0 x or 0xfc
rev 1.1 / oct. 2013 28 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) truth tables operation or timing that is not specified is illegal and after such an event, in order to gu arantee proper operation, the lpddr3 device must be powered down and then restarted th rough the specified initialization sequence before normal operation can continue. command truth table command sdr command pins (2) ddr ca pins (10) ck_t edge cke cs_n ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 ck_t(n-1) ck_t(n) mrw h h l l l l l ma0 ma1 ma2 ma3 ma4 ma5 rising x ma6 ma7 op0 op1 op2 op3 op4 op5 op6 op7 falling mrr h h l l l l h ma0 ma1 ma2 ma3 ma4 ma5 rising x ma6 ma7 x falling refresh (per bank) h h l l l h l x rising x x falling refresh (all bank) h h l l l h h x rising x x falling enter self refresh h l l l l h x rising x x falling active (bank) h h l l h r8 r9 r10 r11 r12 ba0 ba1 ba2 rising x r0 r1 r2 r3 r4 r5 r6 r7 r13 r14 falling write (bank) h h l h l l rfu rfu c1 c2 ba0 ba1 ba2 rising x ap 3 c3 c4 c5 c6 c7 c8 c9 c10 c11 falling read (bank) h h l h l h rfu rfu c1 c2 ba0 ba1 ba2 rising x ap 3 c3 c4 c5 c6 c7 c8 c9 c10 c11 falling precharge (per bank, all bank) 11 h h l h h l h ab x x ba0 ba1 ba2 rising x x x x x x x x x x x falling enter deep power down h l l h h l x rising x x falling nop h h l h h h x rising x x falling maintain sref, pd, dpd (nop) 4 l l l h h h x rising x x falling nop h h h x rising x x falling maintain pd, sref, dpd (nop) 4 l l x x rising x x falling enter power down h l h x rising x x falling exit pd, sref, dpd l h h x rising x x falling
rev 1.1 / oct. 2013 29 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. all lpddr3 commands are defined by stat es of cs_n, ca0, ca1, ca 2, ca3, and cke at the rising edge of the clock. 2. bank addresses ba0, ba1, ba2 (ba) determine which bank is to be operated upon. 3. ap "high" during a read or write command indicates that an auto-prech arge will occur to the bank associated with the read or write command. 4. "x" means "h or l (but a defined logic level)", except when the lpddr3 sdram is in pd, sref, or dpd, in which case cs_n, ck_ t/ ck_c, and ca can be floated after the required tcpded time is sa tisfied, and until the required exit procedure is initiated as described in the respective entry/exit procedure. 5. self refresh exit and deep po wer down exit are asynchronous. 6. vref must be between 0 and vddq during self refresh and deep power down operation. 7. caxr refers to command/address bit "x" on the rising edge of clock. 8. caxf refers to command/address bit "x" on the falling edge of clock. 9. cs_n and cke are sampled at the rising edge of clock. 10. the least-significant column address c0 is not tran smitted on the ca bus, and is implied to be zero. 11. ab "high"during precharge command indicates that all bank precharge will occur. in this case, bank address is do-not-care. 12. when cs_n is high, lpddr3 ca bus can be floated.
rev 1.1 / oct. 2013 30 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) cke truth table note: 1. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 2. 'x' means 'don't care'. 3. "current state" is the state of the lpdd r3 device immediately prior to clock edge n. 4. "cken" is the logic state of cke at clock rising edge n; "cken-1" was the state of cke at the previous clock edge. 5. "cs_n" is the logic state of cs_n at the clock rising edge n. 6. "command n" is the command registered at clock edge n, and "operation n" is a result of "command n". 7. power down exit time (txp) should el apse before a command other than nop is issued. the clock must toggle at least twice during the txp period. 8. self-refresh exit time (txsr) should elapse before a comma nd other than nop is issued. th e clock must toggle at least twice during the txsr time. 9. the deep power-down exit procedure mu st be followed as discussed in the deep power-down section of the functional description. 10. upon exiting resetting power down, the device will return to the idle state if tinit5 has expired. 11. in the case of odt disabled, all dq output shall be hi-z . in the case of odt enabled, all dq shall be terminated to vddq. current state 3 cke n-1 4 cke n 4 cs_n 5 command n 6 operation n 6 next state notes active power down llx x maintain active power down active powe down l h h nop exit active power down active 7 idl power down llx x maintain idle power down idle power down l h h nop exit idle power down idle 7 resetting power down llx x maintain resetting power down resetting power down l h h nop exit resetting power down idle or resetting 7,10 deep power down llx x maintain deep power down deep power down l h h nop exit deep power down power on 9 self refresh l l x x maintain self refresh self refresh lhh nop exit self refresh idle 8 bank(s) active h l h nop enter active power down active power- down all banks idle hlh nop enter idle power down idle power down 11 hll enter self refresh enter self refresh self refresh hll deep power down enter deep power down deep power down resetting h l h nop enter resetting power down resetting power down h h refer to the command truth table
rev 1.1 / oct. 2013 31 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) current state bank n - command to bank n note: 1. the table applies when both cke n-1 and cke n are high, and after txsr or txp has been met if the previous state was power down. 2. all states and sequences not shown are illegal or reserved. 3. current state definitions: idle: the bank or banks have been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts / accesses and no register accesses are in progress. reading: a read burst has been initia ted, with auto precharge disabled. writing: a write burst has been initia ted, with auto precharge disabled. 4. the following states must not be interrupted by a command is sued to the same bank. nop commands or allowable commands to the other bank should be issued on any cl ock edge occurring during these states. al lowable commands to the other banks are dete r- mined by its current state and table ?current state bank n - command to bank n?, and according to table ?current state bank n - command to bank m?. precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be in the ?active? state. read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. current state command operation next state note any nop continue previous operation current state idle activate select and activate row active refresh (per bank) begin to refresh refreshing (per bank) 6 refresh (all bank) begin to refresh refreshing (all bank) 7 mrw write value to mode register mr writing 7 mrr read value from mode register idle mr reading reset begin device auto-initialization resetting 8 precharge deactive row in bank or banks precharging 9, 12 row active read select column, and start read burst reading write select column, and start write burst writing mrr read value from mode register active mr reading precharge deactivate row in bank or banks precharging 9 reading read select column, and start new read burst reading 10,11 write select column, and start write burst writing 10,11,13 writing write select column, and start new write burst writing 10,11 read select column, and start read burst reading 10,11,14 power on reset begin device auto-initialization resetting 7, 9 resetting mrr read value from mode register resetting mr reading
rev 1.1 / oct. 2013 32 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) 5. the following states must not be interru pted by any executable command; nop commands must be applied to each positive clock edge during these states. refreshing (per bank): starts with registration of a refresh (per bank) command and ends when trfcpb is met. once trfcpb is met, the bank will be in an ?idle? state. refreshing (all bank): starts with registration of a refresh(al l bank) command and ends when tr fcab is met. once trfcab is met, the device will be in an ?all banks idle? state. idle mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the idle state. resetting mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the resetting state. active mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the row active state. mr writing: starts with the registration of a mrw command and ends when tmrw has been met. once tmrw has been met, the bank will be in the idle state. precharging all: starts with the registration of a precharge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 6. bank-specific; requires that the bank is idle and no bursts are in progress. 7. not bank-specific; requires that all banks are idle and no bursts are in progress. 8. not bank-specific reset command is achieved through mode register write command. 9. this command may or may not be bank specific. if all banks ar e being precharged, they must be in a valid state for prechargi ng. 10. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 11. the new read or write command could be auto precharge enabled or auto precharge disabled. 12. if a precharge command is issued to a bank in the idle state, trp shall still apply. 13. a write command may be applied after the completion of the read burst, burst terminates are not permitted. 14. a read command may be applied after the completion of the write burst, burst terminates are not permitted.
rev 1.1 / oct. 2013 33 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) current state bank n - command to bank m note: 1. the table applies when both cke n-1 and cke n are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. all states and sequences not shown are illegal or reserved. 3. current state definitions: idle: the bank has been precharged, and trp has been met. active: a row in the bank has been activate d, and trcd has been met. no data bursts /accesses and no register accesses are in progress. reading: a read burst has been initia ted, with auto precharge disabled. writing: a write burst has been initia ted, with auto precharge disabled. 4. refresh, self refresh, and mode register write commands may only be issued when all bank are idle. current state of bank n command for bank m operation next state for bank m note any nop continue previous operation current state of bank m idle any any command allowed to bank m - row activating, active, or precharging activate select and activate row in bank m active 6 read select column, and start read burst from bank m reading 7 write select column, and start write burst to bank m writing 7 precharge deactivate row in bank or banks precharging 8 mrr read value from mode register idle mr reading or active mr reading 9,10,12 reading (autoprecharge disabled) read select column, and start read burst from bank m reading 7 write select column, and start write burst to bank m writing 7,15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 8 writing (autoprecharge disabled) read select column, and start read burst from bank m reading 7,16 write select column, and start write burst to bank m writing 7 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 8 reading with autoprecharge read select column, and start read burst from bank m reading 7,13 write select column, and start writ e burst to bank m writing 7,15,13 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 8 writing with autoprecharge read select column, and start read burst from bank m reading 7,13,16 write select column, and start write burst to bank m writing 7,13 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 8 power on reset begin device auto-initialization resetting 11, 14 resetting mrr read value from mode register resetting mr reading
rev 1.1 / oct. 2013 34 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) 5. the following states must not be interrupted by any executab le command; nop commands must be applied during each clock cycle while in these states: idle mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the idle state. resetting mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the resetting state. active mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the row active state. mr writing: starts with the registration of a mrw command and ends when tmrw has been met. once tmrw has been met, the bank will be in the idle state. 6. trrd must be met between activate command to bank n and a subsequent activate command to bank m. 7. reads or writes listed in the command column include reads and writes with auto precharg e enabled and reads and writes with auto precharge disabled. 8. this command may or may not be bank specific. if all banks ar e being precharged, they must be in a valid state for prechargi ng. 9. mrr is allowed during the row activating state and mrw is prohibited during the row activating state. (row activating starts with registration of an activate comma nd and ends when trcd is met.) 10. mrr is allowed during the precharging st ate. (precharging star ts with registration of a prec harge command and ends when trp is met. 11. not bank-specific; requires that all banks are idle and no bursts are in progress. 12. the next state for bank m depends on the current state of ba nk m (idle, row activating, precharging, or active). the reader shall note that the state may be in transition when a mrr is issued. therefore, if bank m is in the row activating state and precharg ing, the next state may be active and precharge dependent upon trcd and trp respectively. 13. read with auto precharge enabled or a write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions in the section of precharge and auto precharg e clarification are followed. 14. reset command is achieved through mode register write command. 15. a write command may be applied after the completion of the read burst, burst terminates are not permitted. 16. a read command may be applied after the completion of the write burst, burst terminates are not permitted.
rev 1.1 / oct. 2013 35 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) data mask truth table note: 1. used to mask write data, provided coincident with the corresponding data. function dm dq note write enable l valid 1 write inhibit h x 1
rev 1.1 / oct. 2013 36 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) absolute maximum dc ratings stresses greater than those listed may cause permanent damage to the device. this is a st ress rating only, and func- tional operation of the device at these or any other conditio ns above those indicated in th e operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1.see the section ?power-up, initialization, and po wer-off? for relationships between power supplies. 2. vrefca ? 0.6 x vddca; however, vrefca may be ? vddca provided that vrefca ? 300mv. 3. vrefdq ?? 0.7 x vddq; however, vrefdq may be ? vddq provided that vrefdq ? 300mv. 4. storage temperature is the case surface temperature on the ce nter/top side of the device. for the measurement conditions, pl ease refer to jesd51-2 standard. parameter symbol min max unit notes vdd1 supply voltage relative to vss vdd1 -0.4 2.3 v 1 vdd2 supply voltage relative to vss vdd2 -0.4 1.6 v 1 vddca supply voltage relative to vssca vddca -0.4 1.6 v 1, 2 vddq supply voltage relative to vssq vddq -0.4 1.6 v 1, 3 voltage on any pin relative to vss vin, vout -0.4 1.6 v storage temperature tstg -55 125 o c 4
rev 1.1 / oct. 2013 37 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac and dc operating conditions operation or timing that is not specified is illegal, and after such an event, in order to gu arantee proper operation, the lpddr3 device must be powered down and then restarted th rough the specialized initialization sequence before normal operation can continue. recommended dc operating conditions note : 1. vdd1 uses significantly less current than vdd2. 2. the voltage range is for dc voltage only. dc is defined as the voltage supplied at the dram and is inclusive of all noise up to 1mhz at the dram package ball. input leakage current note : 1. for ca, cke, cs_n, ck_t, ck_c. any input 0v ? vin ? vddca(all other pins not under test = 0v) 2. although dm is for input only, the dm leakage shall match the dq and dqs_t/dqs_c output leakage specification. 3. the minimum limit requirement is for te sting purposes. the leakage current on vref ca and vrefdq pins should be minimal. 4. vrefdq = vddq/2 or vrefca = vddca/2. (all other pins not under test = 0v) operating temperature note : 1. operating temperature is the case surfac e temperature on the center-t op side of the lpddr3 device. for the measurement condi - tions, please refer to jesd51-2 standard. 2. some applications require operation of lpddr3 in the maximu m temperature conditons in the el evated temperature range between 85c and 105c case temperature. for lpddr3 devices, derating may be neccessary to operate in this range. see mr4 on the sectio n "mode register". 3. either the device case temperature rating or the temperature sensor (see the section of "temperature sensor") may be used to set an appropriate refresh rate, determine the n eed for ac timing de-rating and/or monito r the operating temperature. when using th e temperature sensor, the actual device case temperature may be higher than the toper ra ting that applies for the standard or ele vated temperature ranges. for example, tcase may be above 85c when th e temperature sensor indicates a temperature of less than 85c. parameter symbol min typ max unit core power 1 vdd1 1.70 1.80 1.95 v core power 2 vdd2 1.14 1.20 1.30 v input buffer power vddca 1.14 1.20 1.30 v i/o buffer power vddq 1.14 1.20 1.30 v parameter symbol min max unit note input leakage current il -2 2 ua 2 vref supply leakage current ivref -1 1 ua 1 parameter symbol min max unit note operating temperature standard t oper -30 85 o c 1 extended 85 105 1
rev 1.1 / oct. 2013 38 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac and dc input measurement levels ac and dc logic input levels for single-ended ca and cs_n signals note: 1. for ca and cs_n input only pins. vref = vrefca(dc). 2. see the section ?overshoot and undershoot specifications?. 3. the ac peak noise on vrefca may not allow vrefca to devi ate from vrefca(dc) by more than +/-1% vddca (for reference: approx. +/- 12 mv). 4. for reference: approx. vddca/2 +/- 12 mv. ac and dc logic input levels for cke note: 1. see the section ?overshoot and undershoot specifications?. ac and dc logic input levels for si ngle-ended data (dq and dm) signals note: 1. for dq input only pins. vref = vrefdq(dc). 2. see the section of overshoot and undershoot specifications. 3. the ac peak noise on vrefdq may not allow vrefdq to deviate from vrefdq(dc) by more than +/-1% vddq (for reference: approx. +/- 12 mv). 4. for reference: approx. vddq/2 +/- 12 mv. 5. for reference: approx. vodtr/2 +/- 12 mv. 6. the nominal mode register programmed va lue for rodt and the nominal controller outp ut impedance ron are used for the calcu- lation of vodtr. for testing purp oses a controller ron value of 50 ? is used. vodtr = (2 * ron + rtt) / (ron + rtt) * vddq parameter symbol lpddr3 1866 lpddr3 1600/1333 unit note min max min max ac input logic high vihca vref + 0.135 note 2 vref + 0.150 note 2 v 1,2 ac input logic low vilca note 2 vref - 0.135 note 2 vref - 0.150 v 1,2 dc input logic high vihca vref + 0.100 vddca vref + 0.100 vddca v 1 dc input logic low vilca vssca vref - 0.100 vssca vref - 0.100 v 1 reference voltage for ca and cs_n inputs vrefca(dc) 0.49 * vddca 0.51 * vddca 0.49 * vddca 0.51 * vddca v 3,4 parameter symbol min max unit note cke input high level vihcke 0.65 * vddca note 1 v 1 cke input low level vilcke note 1 0.35 * vddca v 1 parameter symbol lpddr3 1866 lpddr3 1600/1333 unit note min max min max ac input high voltage vihdq vref + 0.135 note 2 vref + 0.150 note 2 v 1,2 ac input low voltage vildq note 2 vref - 0.135 note 2 vref - 0.150 v 1,2 dc input high voltage vihdq vref + 0.100 vddca vref + 0.100 vddq v 1 dc input low voltage vildq vssca vref - 0.100 vssca vref - 0.100 v 1 reference voltage for dq and dm inputs vrefdq(dc) (dq odt dis- abled) 0.49 * vddq 0.51*vddq 0.49 * vddq 0.51*vddq v 3,4 reference voltage for dq and dm inputs vrefdq(dc) (dq odt enabled) vodtr/2 - 0.01*vddq vodtr/2 + 0.01*vddq 0.5 * vodtr - 0.01 * vddq 0.5 * vodtr + 0.01 * vddq v 3,5,6
rev 1.1 / oct. 2013 39 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) vref tolerances the dc-tolerance limits and ac-noise limits for the referenc e voltages vrefca and vrefdq are illustrated in figure be- low. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vdd stands for vddcs for vrefca and vddq for vrefdq. vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of vddca or vddq also over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table ?electrical characteristics and operating conditions?. furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/- 1% vdd. vref(t) cannot track noise on vddq or vddca if th is would send vref outside these specifications. figure. illustration of vref(dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref " shall be understood as vref(dc), as defined in figure above. this clarifies that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which se tup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum positi on within the data-eye of the input signals. this also clarifies that the lpddr3 setu p/hold specification and derating values need to include time and voltage asso- ciated with vref ac-noise. timing and voltage effects due to ac-noise on vref up to th e specified limit (+/-1% of vdd) are included in lpddr3 timings and their associated deratings. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev 1.1 / oct. 2013 40 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) input signal figure. lpddr3 input signal note: 1. numbers reflect nominal values. 2. for ca0-9, ck_t, ck_c and cs_n, vdd stands for vddca. for dq, dm/dnv, dqs_t and dqs_c, vdd stands for vddq. 3. for ca0-9, ck_t, ck_c and cs_n, vss stands for vssca. for dq, dm/dnv, dqs_t and dqs_c, vss stands for vssq.
rev 1.1 / oct. 2013 41 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac and dc logic input levels for differential signals differential signal definition figure. definition of differential ac-swing and time above ac-level tdvac v ihdiff(ac) min v ihdiff(dc) min v ildiff(dc) max v ildiff(ac) max 0.0 ck_t - ck_c dqs_t - dqs_c half cycle t dvac t dvac differential time voltage
rev 1.1 / oct. 2013 42 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) differential swing requirem ents for clock and strobe note: 1. used to define a differential signal sl ew-rate. for ck_t - ck_c use vih/vil(dc) of ca and vrefca; for dqs_t - dqs_c, use vih / vil(dc) of dqs and vrefdq; if a reduced dc-high or dc-low level is used for a signal group, th en the reduced level applies also here. 2. for ck_t - ck_c use vih/vil(ac) of ca and vrefca; for dqs_t - dqs_c, use vih/vil(ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however th e single-ended signals ck_t, ck_c, dqs_t, and dqs_c need to be within the respective limits (vih(dc) max, vil(dc)min ) for single-ended signals as well as the limitations for overshoot and undershoot. refer to the section of ?overshoot and undershoot specifications?. 4. for ck_t and ck_c, vref = vrefca(dc). for dqs_t and dqs_c, vref = vrefdq(dc). table. allowed time before ring back (tdvac) for dqs_t - dqs_c table. allowed time before ri ngback (tdvac) for ck_t - ck_c parameter symbol min max unit note dc differential input high vihdiff(dc) 2 x (vih(dc) - vref) note 3 v 1 dc differential input low vildiff(dc) note 3 2 x (vil(dc) - vref) v 1 ac differential input high vihdiff( ac) 2 x (vih(ac) - vref) note 3 v 2 ac differential input low vildiff(ac ) note 3 2 x (vil(ac) - vref) v 2 slew rate [v/ns] t dvac [ps] @ |vih/ldiff(ac)| = 270mv t dvac [ps] @ |vih/ldiff(ac)| = 300mv t dvac [ps] @ |vih/ldiff(ac)| = 300mv 1866mbps 1600mbps 1333mbps min min min > 8.0 40 48 58 8.0 40 48 58 7.0 39 46 56 6.0 36 43 53 5.0 33 40 50 4.0 29 35 45 3.0 21 27 37 <3.0 21 27 37 slew rate [v/ns] t dvac [ps] @ |vih/ldiff(ac)| = 270mv t dvac [ps] @ |vih/ldiff(ac)| = 300mv t dvac [ps] @ |vih/ldiff(ac)| = 300mv 1866mbps 1600mbps 1333mbps min min min > 8.0 40 48 58 8.0 40 48 58 7.0 39 46 56 6.0 36 43 53 5.0 33 40 50 4.0 29 35 45 3.0 21 27 37 <3.0 21 27 37
rev 1.1 / oct. 2013 43 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) single-ended requirements for differential signals each individual component of a differential signal (ck_ t, dqs_t, ck_c, or dqs_c) has also to comply with certain requirements for single-ended signals. ck_t and ck_c shall meet vseh(ac)mi n / vsel(ac)max in every half-cycle. dqs_t, dqs_c shall meet vseh(ac)min / vsel(ac)ma x in every half-cycle proceeding and following a valid transition. note that the applicable ac-levels for ca and dq's are different per speed-bin. figure. single-ended requirement for differential signals note that while ca and dq signal requirements are wi th respect to vref, the single-ended components of differential signals have a requirement with respect to vddq/2 for dqs_t, dqs_c and vddca/2 for ck_t, ck_c; this is nominally the same. the transition of si ngle-ended signals through the ac-levels is used to measure setup time. for single-ended components of differential signals the requirement to reach vsel(ac)max, vseh(ac)min has no bearing on timing , but adds a restriction on the common mode char- acteristics of these signals. vssca or vssq vddca or vddq vsel(ac)max vseh(ac)min vseh(ac) vsel(ac) time vddca/2 or vddq/2 ck_t, ck_c dqs_t, or dqs_c
rev 1.1 / oct. 2013 44 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. single-ended levels for clock and strobe note: 1. for ck_t, ck_c use vseh/vsel(ac) of ca; for strobes (dqs 0_t, dqs0_c, dqs1_t, dqs1_c, dq s2_t, dqs2_c, dqs3_t, dqs3_c) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vseh(ac)/vsel(ac) for ca is based on vrefca; if a reduced ac-high or ac-low leve l is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however the single-ended signals ck_t, ck_c, dqs0_t , dqs0_c, dqs1_t, dqs 1_c, dqs2_t, dqs2_c, dqs3_t, dqs3_c need to be within the respective limits (vih(dc) max, vil(dc)min) for single-ended signals as well as the limita tions for overshoot and undershoot. refer to the section of overshoot and undershoot specifications. parameter symbol min max unit note single-ended high level for strobes vseh (ac150) (vddq/2) + 0.150 note 3 v 1, 2 single-ended high level for ck_t and ck_c (vddca/2) + 0.150 note 3 v 1, 2 single-ended low level for strobes vsel (ac150) note 3 (vddq / 2) - 0.150 v1, 2 single-ended low level for ck_t and ck_c note 3 (vddca / 2) - 0.150 v1, 2 single-ended high level for strobes vseh (ac135) (vddq/2) + 0.135 note 3 v 1, 2 single-ended high level for ck_t and ck_c (vddca/2) + 0.135 note 3 v 1, 2 single-ended low level for strobes vsel (ac135) note 3 (vddq / 2) - 0.135 v1, 2 single-ended low level for ck_t and ck_c note 3 (vddca / 2) - 0.135 v1, 2
rev 1.1 / oct. 2013 45 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) differential input cross point voltage to guarantee tight setup and hold times as well as output sk ew parameters with respect to clock and strobe, each cross point voltage of differential input si gnals (ck_t, ck_c and dqs_t, dqs_c) must meet the requirements in ? single-end- ed levels for clock and strobe? . the differential input cros s point voltage vix is measured from the actual cross point of true and complement signals to the midlevel between of vdd and vss. figure. vix definition table. cross point voltage for differen tial input signals (clock and strobe) note: 1. the typical value of vix(ac) is expected to be about 0.5 x vdd of the transmitting device, and vix(ac) is expected to track variations in vdd. vix(ac) indicates the voltage at which differential input signals must cross. 2. for ck_t and ck_c, vref = vrefca(dc). for dqs_t and dqs_c, vref = vrefdq(dc). parameter symbol min max unit note differential input cross point voltage relative to vddca/2 for ck_t and ck_c vixca -120 120 mv 1, 2 differential input cross point voltage relative to vddq/2 for dqs_t and dqs_c vixdq -120 120 mv 1, 2 vddca or vddq vssca or vssq vddca/2 or vddq/2 v ix v ix v ix ck_c, dqs_c ck_t, dqs_t
rev 1.1 / oct. 2013 46 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) slew rate definitions for single-ended input signals see "ca and cs_n setup, hold and derating" for single-end ed slew rate definitions for address and command signals. see "data setup, hold and slew rate derating" for si ngle-ended slew rate definitions for data signals. slew rate definitions for differential input signals input slew rate for differential signals (ck_t, ck_c and dq s_t, dqs_c) are defined and measured as shown in the table and figure below. table. differential inpu t slew rate definition note: 1. the differential signal (i.e. ck_t - ck_c and dq s_t - dqs_c) must be linear between these thresholds. figure. differential input slew rate defi nition for ck_t, ck_c and dqs_t, dqs_c parameter measured defined by from to differential input slew rate for rising edge (ck_t - ck_c and dqs_t - dqs_c) v ildiffmax v ihdiffmin [v ihdiffmin - v ildiffmax ] / delta trdiff differential input slew rate for falling edge (ck_t - ck_c and dqs_t - dqs_c) v ihdiffmin v ildiffmax [v ihdiffmin - v ildiffmax ] / delta tfdiff delta trdiff v ihdiffmin v ildiffmax differential input voltage (i.e. ck_t - ck_c, dqs_t - dqs_c) 0 delta tfdiff
rev 1.1 / oct. 2013 47 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac and dc output measurement levels single ended ac and dc output levels note: 1. ioh = -0.1ma, 2. iol = 0.1ma 3. the min value is derived when using rtt, min an d ron,max (+/- 30% uncalibrated, +/-15% calibrated). differential ac and dc outp ut levels (dqs_t, dqs_c) note: 1. ioh = -0.1ma, 2. iol = 0.1ma parameter symbol levels unit note dc output logic high measurement level (f or iv curve linearity) voh(dc) 0.9 x vddq v 1 dc output logic low measurement level (for iv curve linearity) vol(dc) odt disabled 0.1 x vddq v 2 vol(dc) odt enabled vddq * [0.1 + 0.9 * (ron/ (rtt+ron))] v3 ac output logic high measurement level (for output slew rate) voh(ac) vrefdq + 0.12 v ac output logic low measurement level (for output slew rate) vol(ac) vrefdq - 0.12 v output leakage current (dq, dm, dqs_t and dqs_c) (dq, dqs_t and dqs_c are disabled; 0v ? vout ? vddq) min i oz -5 ua max 5 ua delta ron between pull-up and pull-down for dq and dm min mm pupd -15 % max 15 % parameter symbol levels unit note ac differential output high measurement leve l (for output sr) vohdiff(ac) + 0.20 x vddq v ac differential output low measurement level (for output sr) voldiff(ac) - 0.20 x vddq v
rev 1.1 / oct. 2013 48 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) single ended output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and mea- sured between vol(ac) and voh(ac) for single ended signals as shown in below table and figure. note: output slew rate is verified by design and characterization and may not be subject to production test. figure. single ended output slew rate definition table. output slew rate (single ended ) description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals note: 1. measured with output reference load. 2. the ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature a nd volt- age range. for a given output, it represents the maximum differe nce between pull-up and pull-down drivers due to process variat ion. 3. the output slew rate for fallin g and rising edges is defined and me asured between vol(ac) and voh(ac). 4. slew rates are measured under average sso conditions, with 50% of dq signals per data byte switching. parameter measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac) - vol(ac)] / delta trse single ended output slew rate for falling edge voh(ac) vol(ac) [voh(ac) - vol(ac)] / delta tfse parameter symbol min max unit note single-ended output slew rate (ron = 40 ? +/- 30%) srqse 1.5 4.0 v/ns output slew-rate matching ratio (pull-up to pull-down) 0.7 1.4 delta trse v oh(ac) v ol(ac) single ended output voltage (i.e. dq) v ref delta tfse
rev 1.1 / oct. 2013 49 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differentia l signals as shown in below table and figure. note: 1. output slew rate is verified by design and ch aracterization, and may not be subject to production test. figure. differential output slew rate definition table. output slew rate (differential ) description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff: differential signals note: 1. measured with output reference load. 2. the output slew rate for fallin g and rising edges is defined and me asured between vol(ac) and voh(ac). 3. slew rates are measured under av erage sso conditions, with 50% of dq signals per data byte switching. parameter measured defined by from to differential output slew rate for rising edge v oldiff(ac) v ohdiff(ac) [v ohdiff(ac) - v oldiff(ac) ] / delta trdiff differential output slew rate for falling edge v ohdiff(ac) v oldiff(ac) [v ohdiff(ac) - v oldiff(ac) ] / delta tfdiff parameter symbol min max unit note differential output slew rate (ron = 40 ? +/- 30%) srqdiff 3.0 8.0 v/ns v ohdiff(ac) v oldiff(ac) differential output voltage (i.e. dqs_t - dqs_c) 0 delta tfdiff delta trdiff
rev 1.1 / oct. 2013 50 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) overshoot and undershoot specifications figure. overshoot and undershoot definition note: 1. vdd stands for vddca for ca0-9, ck_t, ck_c, cs_n, and cke. vdd stands for vddq for dq, dm, odt, dqs_t, and dqs_c. 2. vss stands for vssca for ca0-9, ck_t , ck_c, cs_n, and cke. vss stands for vssq for dq, dm, odt, dqs_t, and dqs_c. 3. absolute maximum requirements apply. 4. maximum peak amplitude values are refe renced from actual vdd and vss values. 5. maximum area values are referenced fr om maximum operating vdd and vss values. parameter 1866 1600 1333 unit maximum peak amplitude allowed for overshoot area 0.35 v maximum peak amplitude allowe d for undershoot area 0.35 v maximum overshoot area above vdd 0.09 0.10 0.12 v-ns maximum undershoot area below vss 0.09 0.10 0.12 v-ns maximum amplitude vdd vss overshoot area undershoot area time (ns) volts (v)
rev 1.1 / oct. 2013 51 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) output buffer characteristics hsul_12 driver output timing reference load these ?timing reference loads? are not intended as a precis e representation of any particular system environment or a depiction of the actual load presented by a production te ster. system designers should use ibis or other simulation tools to correlate the timing reference lo ad to a system environment. manufacture rs correlate to their production test conditions, generally one or more coaxial transmi ssion lines terminated at the tester electronics. note: 1. all output timing parameter values (like t dqsck , t dqsq , t qhs, t hz , t rpre etc.) are reported with resp ect to this reference load. this reference load is also used to report slew rate. figure. hsul_12 driver output reference load for timing and slew rate ron pu and ron pd resistor definition note 1: this is under the condition that ron pd is turned off note 1: this is under the condition that ron pu is turned off figure. output driver: definition of voltages and currents output vref lpddr3 0.5 x vddq sdram cload = 5pf rtt = 50 ? vtt = 0.5 x vddq vddq vssq dq ron pu ron pd to other circuitry like rcv, ... chip in drive mode output driver v out i out i pu i pd
rev 1.1 / oct. 2013 52 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ron pu and ron pd characteristics with zq calibration output driver impedance ron is defined by the value of the external reference resistor rzq. nominal rzq is 240 ? . table - output driver dc electrical characteristics with zq calibration note: 1. across entire operating temperature range, after calibration. 2. rzq = 240 ? . 3. the tolerance limits are specified after calibration with fixed voltage and temperature. for behavior of the toler- ance limits if temperature or voltage changes after cali bration, see following section on voltage and temperature sensitivity. 4. pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x vddq. 5. measurement definition for mismat ch between pull-up and pull-down, mmpupd: measure ron pu and ron pd , both at 0.5 x vddq: for example, with mmpupd(max) = 15% and ronpd = 0.85, ronpu must be less than 1.0. 6. output driver strength measured without odt. ron nom resistor vout min typ max unit notes 34.3 ? ron34pd 0.5 x vddq 0.85 1.00 1.15 rzq/7 1,2,3,4 ron34pu 0.5 x vddq 0.85 1.00 1.15 rzq/7 1,2,3,4 40.0 ? ron40pd 0.5 x vddq 0.85 1.00 1.15 rzq/6 1,2,3,4 ron40pu 0.5 x vddq 0.85 1.00 1.15 rzq/6 1,2,3,4 48.0 ? ron48pd 0.5 x vddq 0.85 1.00 1.15 rzq/5 1,2,3,4 ron48pu 0.5 x vddq 0.85 1.00 1.15 rzq/5 1,2,3,4 mismatch between pull-up and pull-down mm pupd -15.00 +15.00 % 1,2,3,4,5
rev 1.1 / oct. 2013 53 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) output driver temperatur e and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen a ccording to the tables shown below. table. output driver sensitivity definition note 1. t = t - t (@ calibration), v = v - v (@ calibration) 2. drondt and drondv are not subjec t to production test but are verifi ed by design and characterization. table. output driver temper ature and voltage sensitivity ron pu and ron pd characteristics without zq calibration output driver impedance ron is defined by desi gn and characterization as default setting. table. output driver dc electrical characteristics without zq calibration note: 1. across entire operating temper ature range, without calibration. resistor vout min max unit notes ronpd 0.5 x vddq 85 - ( drondt x | t |) - ( drondv x| v |) 115 + ( drondt x | t |) + ( drondv x| v |) % 1,2 ronpu rtt 0.5 x vddq 85 - ( drttdt x | t |) - ( drttdv x| v |) 115 + ( drttdt x | t |) + ( drttdv x| v |) %1,2 symbol parameter min max unit drondt ron temperature sensitivity 0.00 0.75 % / c drondv ron voltage sensitivity 0.00 0.20 % / mv drttdt rtt temperature sensitivity 0.00 0.75 % / c drttdv rtt voltage sensitivity 0.00 0.20 % / mv ron nom resistor vout min nom max unit notes 34.3 ? ron40pd 0.5 x vddq 24 34.3 44.6 ? 1 ron40pu 0.5 x vddq 24 34.3 44.6 ? 1 40.0 ? ron40pd 0.5 x vddq 28 40 52 ? 1 ron40pu 0.5 x vddq 28 40 52 ? 1 48.0 ? ron48pd 0.5 x vddq 33.6 48 62.4 ? 1 ron48pu 0.5 x vddq 33.6 48 62.4 ? 1 60.0 ?? (optional) ron60pd 0.5 x vddq 42 60 78 ? 1 ron60pu 0.5 x vddq 42 60 78 ? 1 80.0 ?? (optional) ron80pd 0.5 x vddq 56 80 104 ? 1 ron80pu 0.5 x vddq 56 80 104 ? 1
rev 1.1 / oct. 2013 54 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) rzq i-v curve table. rzq i-v curve voltage(v) ron = 240 ?? (rzq) pull-down pull-up current [ma] / ron [ ? ] current [ma] / ron [ ? ] default value after zqreset with calibration default value after zqreset with calibration min max min max min max min max [ma] [ma] [ma] [ma] [ma] [ma] [ma] [ma] 0.00 0.00 0.00 n/a n/a 0.00 0.00 n/a n/a 0.05 0.17 0.35 n/a n/a -0.17 -0.35 n/a n/a 0.10 0.34 0.70 n/a n/a -0.34 -0.70 n/a n/a 0.15 0.50 1.03 n/a n/a -0.50 -1.03 n/a n/a 0.20 0.67 1.39 n/a n/a -0.67 -1.39 n/a n/a 0.25 0.83 1.73 n/a n/a -0.83 -1.73 n/a n/a 0.30 0.97 2.05 n/a n/a -0.97 -2.05 n/a n/a 0.35 1.13 2.39 n/a n/a -1.13 -2.39 n/a n/a 0.40 1.26 2.71 n/a n/a -1.26 -2.71 n/a n/a 0.45 1.39 3.01 n/a n/a -1.39 -3.01 n/a n/a 0.50 1.51 3.32 n/a n/a -1.51 -3.32 n/a n/a 0.55 1.63 3.63 n/a n/a -1.63 -3.63 n/a n/a 0.60 1.73 3.93 2.17 2.94 -1.73 -3.93 -2.17 -2.94 0.65 1.82 4.21 n/a n/a -1.82 -4.21 n/a n/a 0.70 1.90 4.49 n/a n/a -1.90 -4.49 n/a n/a 0.75 1.97 4.74 n/a n/a -1.97 -4.74 n/a n/a 0.80 2.03 4.99 n/a n/a -2.03 -4.99 n/a n/a 0.85 2.07 5.21 n/a n/a -2.07 -5.21 n/a n/a 0.90 2.11 5.41 n/a n/a -2.11 -5.41 n/a n/a 0.95 2.13 5.59 n/a n/a -2.13 -5.59 n/a n/a 1.00 2.17 5.72 n/a n/a -2.17 -5.72 n/a n/a 1.05 2.19 5.84 n/a n/a -2.19 -5.84 n/a n/a 1.10 2.21 5.95 n/a n/a -2.21 -5.95 n/a n/a 1.15 2.23 6.03 n/a n/a -2.23 -6.03 n/a n/a 1.20 2.25 6.11 n/a n/a -2.25 -6.11 n/a n/a
rev 1.1 / oct. 2013 55 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. i-v curve after zq reset figure. i-v curve after calibration
rev 1.1 / oct. 2013 56 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) odt levels and i-v characteristics on-die termination effective resistance, rtt, is defined by mode register mr11[1:0]. odt is applied to the dq, dm, and dqs_t/dqs_c pins. a functional representation of the on-d ie termination is shown in the figure below. rtt is de- fined by the following formula: rttpu = (vddq - vout) / | iout | table. odt dc electrical characteristics, assu ming rzq = 240 ohm after proper zq calibration rtt (ohm) vout (v) iout min (ma) max (ma) rzq/1 0.6 -2.17 -2.94 rzq/2 0.6 -4.34 -5.88 rzq/4 0.6 -8.68 -11.76 vddq vss dq rtt pu to other circuitry odt v out i out i pu v ddq - v out
rev 1.1 / oct. 2013 57 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) input/output capacitance (toper; vddq = 1.14-1.3v; vddca = 1.14-1.3v; vdd1 = 1.7-1.95v, vdd2 = 1.14-1.3v) note: 1. this parameter applies to die device only (does not include package capacitance). 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147 (procedure for measur ing input capacitance using a vector ne twork analyzer (vna) with vdd1, vdd2, vddq, vss, vssca, vssq applied and all other pins floating). 3. absolute value of cck_t - cck_c. 4. ci applies to cs_n, cke, ca0-ca9. 5. cdi = ci - 0.5 * (cck_t + cck_c) 6. dm loading matches dq and dqs. 7. mr3 i/o configuration ds op3-op0 = 0001b (34.3 ohm typical) 8. absolute value of cdqs_t and cdqs_c. 9. cdio = cio - 0.5 * (cdqs_t + cdqs_c) in byte-lane. parameter symbol min max unit note input capacitance, ck_t and ck_c cck 0.5 1.2 pf 1,2 input capacitance delta, ck_t and ck_c cdck 0 0.15 pf 1,2,3 input capacitance, all other input-only pins ci 0.5 1.1 pf 1,2,4 input capacitance delta, all other input-only pins cdi -0.2 0.2 pf 1,2,5 input/output capacitance, dq, dm, dqs_t, dqs_c cio 1.0 1.8 pf 1,2,6,7 input/output capacitance delta, dqs_t and dqs_c cddqs 0 0.2 pf 1,2,7,8 input/output capacitance delta, dq and dm cdio -0.25 0.25 pf 1,2,7,9 input/output capacitance zq czq 0 2.0 pf 1,2
rev 1.1 / oct. 2013 58 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) idd specification parameters and test conditions idd measurement conditions the following definitions are used within the idd measurement tables: low: v in ?? v il (dc) max high: vin ? v ih (dc) min stable: inputs are stable at a high or low level. switching: see tables below. table. switching for ca input signals note: 1. cs_n must always be driven high. 2. for each clock cycle, 50% of the ca bus is changing between high and low once per clock for the ca bus. 3. the above pattern (n, n+1, n+2, n+3...) is used continuously during idd measurement for idd values that require switching on the ca bus. switching for ca ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) cycle n n+1 n+2 n+3 cs_n high high high high ca0 high low low low low high high high ca1 high high high low low low low high ca2 high low low low low high high high ca3 high high high low low low low high ca4 high low low low low high high high ca5 high high high low low low low high ca6 high low low low low high high high ca7 high high high low low low low high ca8 high low low low low high high high ca9 high high high low low low low high
rev 1.1 / oct. 2013 59 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. switching for idd4r note: 1. data strobe (dqs) is changing be tween high and low every clock cycle. 2. the above pattern (n, n+1, ...) is used continuously during idd measurement for idd4r. clock cke cs_n clock cycle number command ca[0:2] ca[3:9] all dqs rising high low n read_rising hlh lhlhlhl l falling high low n read_falling lll lllllll l rising high high n+1 nop lll lllllll h falling high high n+1 nop lll lllllll l rising high high n+2 nop lll lllllll h falling high high n+2 nop lll lllllll h rising high high n+3 nop lll lllllll h falling high high n+3 nop hlh hlhllhl l rising high low n+4 read_rising hlh hlhllhl h falling high low n+4 read_falling lhh hhhhhhh h rising high high n+5 nop hhh hhhhhhh h falling high high n+5 nop hhh hhhhhhh l rising high high n+6 nop hhh hhhhhhh l falling high high n+6 nop hhh hhhhhhh l rising high high n+7 nop hhh hhhhhhh h falling high high n+7 nop hlh lhlhlhl l
rev 1.1 / oct. 2013 60 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. switching for idd4w note: 1. data strobe (dqs) is changing be tween high and low every clock cycle. 2. data masking (dm) must always be driven low. 3. the above pattern (n, n+1...) is used co ntinuously during idd measurement for idd4w. clock cke cs_n clock cycle number command ca[0:2] ca[3:9] all dqs rising high low n write_rising hll lhlhlhl l falling high low n write_falling lll lllllll l rising high high n+1 nop lll lllllll h falling high high n+1 nop lll lllllll l rising high high n+2 nop lll lllllll h falling high high n+2 nop lll lllllll h rising high high n+3 nop lll lllllll h falling high high n+3 nop hll hlhllhl l rising high low n+4 write_rising hll hlhllhl h falling high low n+4 write_falling lhh hhhhhhh h rising high high n+5 nop hhh hhhhhhh h falling high high n+5 nop hhh hhhhhhh l rising high high n+6 nop hhh hhhhhhh l falling high high n+6 nop hhh hhhhhhh l rising high high n+7 nop hhh hhhhhhh h falling high high n+7 nop hll lhlhlhl l
rev 1.1 / oct. 2013 61 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) idd specifications (1/2) - all values are based on a single die. total current consumption is dependent to user operating condition parameter / condition symbol power supply 1866 1600 unit note operating one bank active-precharge current: tck = tckmin; trc = trcmin; cke is high; cs_n is high between valid commands; ca bus inputs are switching; data bus inputs are stable odt disabled idd0 1 vdd1 8 8 ma idd0 2 vdd2 32 32 ma idd0 in vddca vddq 10 10 ma 4 idle power-down standby current: tck = tckmin; cke is low; cs_n is high; all banks are idle; ca bus inputs are switching; data bus inputs are stable odt disabled idd2p 1 vdd1 0.9 0.9 ma idd2p 2 vdd2 3 3 ma idd2p in vddca vddq 0.2 0.2 ma 4,8 idle power-down standby current with clock stop: ck_t = low, ck_c = high; cke is low; cs_n is high; all banks are idle; ca bus inputs are stable; data bus inputs are stable odt disabled idd2ps 1 vdd1 0.9 0.9 ma idd2ps 2 vdd2 3 3 ma idd2ps in vddca vddq 0.2 0.2 ma 4,8 idle non-power-down standby current: tck = tckmin; cke is high; cs_n is high; all banks are idle; ca bus inputs are switching; data bus inputs are stable odt disabled idd2n 1 vdd1 2 2 ma idd2n 2 vdd2 10 10 ma idd2n in vddca vddq 10 10 ma 4 idle non-power-down standby current with clock stopped: ck_t = low; ck_c = high; cke is high; cs_n is high; all banks are idle; ca bus inputs are stable; data bus inputs are stable odt disabled idd2ns 1 vdd1 1 1 ma idd2ns 2 vdd2 6 6 ma idd2ns in vddca vddq 10 10 ma 4 active power-down standby current: tck = tckmin; cke is low; cs_n is high; one bank is active; ca bus inputs are switching; data bus inputs are stable odt disabled idd3p 1 vdd1 2 2 ma idd3p 2 vdd2 7 7 ma idd3p in vddca vddq 0.2 0.2 ma 4,8 active power-down standby current with clock stop: ck = low, ck# = high; cke is low; cs_n is high; one bank is active; ca bus inputs are stable; data bus inputs are stable odt disabled idd3ps 1 vdd1 2 2 ma idd3ps 2 vdd2 7 7 ma idd3ps in vddca vddq 0.2 0.2 ma 4,8 active non-power-down standby current: tck = tckmin; cke is high; cs_n is high; one bank is active; ca bus inputs are switching; data bus inputs are stable odt disabled idd3n 1 vdd1 2 2 ma idd3n 2 vdd2 10 10 ma idd3n in vddca vddq 10 10 ma 4
rev 1.1 / oct. 2013 62 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) idd specifications (2/2) - all values are based on a single die. total current consumption is dependent to user operating condition parameter / test condition symbol power supply 1866 1600 unit note active non-power-down standby current with clock stopped: ck = low, ck# = high cke is high; cs_n is high; one bank is active; ca bus inputs are stable; data bus inputs are stable odt disabled idd3ns 1 vdd1 2 2 ma idd3ns 2 vdd2 8 8 ma idd3ns in vddca vddq 10 10 ma 4 operating burst read current: tck = tckmin; cs_n is high between valid commands; one bank is active; bl = 8; rl = rl (min); ca bus inputs are switching; 50% data change each burst transfer odt disabled idd4r 1 vdd1 10 8 ma idd4r 2 vdd2 240 200 ma idd4r in vddca 10 10 ma idd4r q vddq 260 200 ma 5 operating burst write current: tck = tckmin; cs_n is high between valid commands; one bank is active; bl = 8; wl = wlmin; ca bus inputs are switching; 50% data change each burst transfer odt disabled idd4w 1 vdd1 10 8 ma idd4w 2 vdd2 260 220 ma idd4w in vddca vddq 30 30 ma 4 all-bank refresh burst current: tck = tckmin; cke is high between valid commands; trc = trfcabmin; burst refresh; ca bus inputs are switching; data bus inputs are stable odt disabled idd5 1 vdd1 40 40 ma idd5 2 vdd2 150 150 ma idd5 in vddca vddq 10 10 ma 4 all-bank refresh average current: tck = tckmin; cke is high between valid commands; trc = trefi; ca bus inputs are switching; data bus inputs are stable odt disabled idd5ab 1 vdd1 3.2 3.2 ma idd5ab 2 vdd2 12 12 ma idd5ab in vddca vddq 10 10 ma 4 per-bank refresh average current: tck = tckmin; cke is high between valid commands; trc = trefi/8; ca bus inputs are switching; data bus inputs are stable odt disabled idd5pb 1 vdd1 3.5 3.5 ma idd5pb 2 vdd2 15 15 ma idd5pb in vddca vddq 10 10 ma 4 self refresh current (?30c to +85c): ck_t = low, ck_c = high; cke is low; ca bus inputs are stable; data bus inputs are stable maximum 1x self refresh rate odt disabled idd6 1 vdd1 3 3 ma 6 idd6 2 vdd2 8 8 ma 6 idd6 in vddca vddq 0.2 0.2 ma 4,6,8 self refresh current (+85c to +105c): ck_t = low, ck_c = high; cke is low; ca bus inputs are stable; data bus inputs are stable odt disabled idd6et 1 vdd1 tbd tbd ma 6,7 idd6et 2 vdd2 tbd tbd ma 6,7 idd6et in vddca vddq tbd tbd ma 4,6,7,8 deep power-down current: ck_t = low, ck_c = high; cke is low; ca bus inputs are stable; data bus inputs are stable odt disabled idd8 1 vdd1 30 30 ua 7 idd8 2 vdd2 70 70 ua 7 idd8 in vddca vddq 100 100 ua 4,7
rev 1.1 / oct. 2013 63 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. published idd values are the maximum of the distribution of the arithmetic mean. 2. idd current specifications are tested after the device is properly initialized. 3. the 1x self refresh rate is the rate at which the device is refreshed internally during self refresh, before going into the elevated temperature range. 4. measured currents are the summation of vddq and vddca. 5. guaranteed by design with output load = tbd pf and ron = 40 ohm. 6. this is the general definition th at applies to full-array self refresh. 7. idd6et is a typical value, is sampled only, and is not tested. 8. for all idd measuremen ts, vihcke = 0.65 x vddca, vilcke = 0.35 x vddca. idd6 partial array self refresh current note: 1. idd6 85 o c is the maximum, and idd6 25 o c is typical value. 2. idd6 currents are measur ed using bank-masking only. 3. idd values published are the maximum of the distribution of the arithmetic mean. t e m p . ( o c) memory array unit 8 banks 4 banks 2 banks 1 bank 25 0.50 / 1.00 / 0.02 tbd tbd tbd ma 85 3.00 / 8.00 / 0.20 tbd tbd tbd ma 105 tbd tbd tbd tbd ma
rev 1.1 / oct. 2013 64 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac timing parameters (1/5) parameter symbol min max lpddr3 1866 lpddr3 1600 lpddr3 1333 unit note maximum clock frequency - 933 800 667 mhz clock timing average clock period tck(avg) min 1.071 1.25 1.5 ns max 100 average high pulse width tch(avg) min 0.45 tck(avg) max 0.55 average low pulse width tcl(avg) min 0.45 tck(avg) max 0.55 absolute clock period tck(abs) min tck(avg)min + tjit(per)min ns absolute clock high pulse width (with allowed jitter) tch(abs), allowed min 0.43 tck(avg) max 0.57 absolute clock low pulse width (with allowed jitter) tcl(abs), allowed min 0.43 tck(avg) max 0.57 clock period jitter (with allowed jitter) tjit(per), allowed min -60 -70 -80 ps max 60 70 80 maximum clock jitter between two consecutive clock cycles (with allowed jitter) tjit(cc), allowed max 120 140 160 ps duty cycle jitter (with allowed jitter) tjit(duty), allowed min min((tch(abs)min - tch(avg)min), (tcl(abs)min - tcl(avg)min)) * tck(avg) ps max max((tch(abs)max - tch(avg)max), (tch(abs)max - tcl(avg)max)) * tck(avg) cumulative error across 2 cycles terr(2per), allowed min -88 -103 -118 ps max 88 103 118 cumulative error across 3 cycles terr(3per), allowed min -105 -122 -140 ps max 105 122 140 cumulative error across 4 cycles terr(4per), allowed min -117 -136 -155 ps max 117 136 155 cumulative error across 5 cycles terr(5per), allowed min -126 -147 -168 ps max 126 147 168 cumulative error across 6 cycles terr(6per), allowed min -133 -155 -177 ps max 133 155 177 cumulative error across 7 cycles terr(7per), allowed min -139 -163 -186 ps max 139 163 186 cumulative error across 8 cycles terr(8per), allowed min -145 -169 -193 ps max 145 169 193 cumulative error across 9 cycles terr(9per), allowed min -150 -175 -200 ps max 150 175 200 cumulative error across 10 cycles terr(10per), allowed min -154 -180 -205 ps max 154 180 205
rev 1.1 / oct. 2013 65 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac timing parameters (2/5) parameter symbol min max lpddr3 1866 lpddr3 1600 lpddr3 1333 unit note clock timing (continued) cumulative error across 11 cycles terr(11per), allowed min -158 -184 -210 ps max 158 184 210 cumulative error across 12 cycles terr(12per), allowed min -161 -188 -215 ps max 161 188 215 cumulative error across n cycles (n = 13, 14 ,. . . ,20) terr(nper), allowed min terr(nper),allowed min = (1 + 0.68ln(n)) * tjit(per),allowed min ps max terr(nper),allowed max = (1 + 0.68ln(n)) * tjit(per),allowed max zq calibration parameters initialization calibration time tzqinit min 1 us long calibration time tzqcl min 360 ns short calibration time tzqcs min 90 ns calibration reset time tzqreset min max(50ns, 3nck) ns read parameters 3 dqs output access time from ck/ck# tdqsck min 2.5 ns max 5.5 dqsck delta short tdqsckds max 190 220 265 ps 4 dqsck delta medium tdqsckdm max 435 511 593 ps 5 dqsck delta long tdqsckdl max 525 614 733 ps 6 dqs-dq skew tdqsq max 115 135 165 ps dqs output high pulse width tqsh min tch(abs) - 0.05 tck(avg) dqs output low pulse width tqsl min tcl(abs) - 0.05 tck(avg) dq/dqs output hold time from dqs tqh min min (tqsh, tqsl) ps read preamble trpre min 0.9 tck(avg) 7,10 read postamble trpst min 0.3 tck(avg) 7,11 dqs low-z from clock tlz(dqs) min tdqsck(min) - 300 ps 7 dq low-z from clock tlz(dq) min tdqsck(min) - 300 ps 7 dqs high-z from clock thz(dqs) max tdqsck(max) - 100 ps 7 dq high-z from clock thz(dq) max tdqsck(max) + (1.4 x tdqsq- max) ps 7
rev 1.1 / oct. 2013 66 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac timing parameters (3/5) parameter symbol min max lpddr3 1866 lpddr3 1600 lpddr3 1333 unit note write parameters 3 dq and dm input setup time (vref based) tds min 130 150 175 ps dq and dm input hold time (vref based) tdh min 130 150 175 ps dq and dm input pulse width tdipw min 0.35 tck(avg) write command to 1st dqs latching transition tdqss min 0.75 tck(avg) max 1.25 dqs input high-lev el width tdqsh min 0.4 tck(avg) dqs input low-level width tdqsl min 0.4 tck(avg) dqs falling edge to ck setup time tdss min 0.2 tck(avg) dqs falling edge hold time from ck tdsh min 0.2 tck(avg) write postamble twpst min 0.4 tck(avg) write preamble twpre min 0.8 tck(avg) cke input parameters cke min. pulse width (high/low pulse width) tcke min max(7.5ns, 3nck) ns cke input setup time tiscke min 0.25 tck(avg) 12 cke input hold time tihcke min 0.25 tck(avg) 13 command path disable delay tcpded min 2 tck(avg) command address input parameters 3 address and control input setup time tisca min 130 150 175 ps 14 address and control input hold time tihca min 130 150 175 ps 14 cs_n input setup time tiscs min 230 270 290 ps 14 cs_n input hold time tihcs min 230 270 290 ps 14 address and control input pulse width tipwca min 0.35 tck(avg) cs_n input pulse width tipwcs min 0.7 tck(avg) boot parameters (10mhz-55mhz) 15,16, 17 clock cycle time tckb min 18 ns max 100 cke input setup time tisckeb min 2.5 ns cke input hold time tihckeb min 2.5 ns address & control input setup time tisb min 1150 ps address & control input hold time tihb min 1150 ps dqs output data access time from ck/ck# tdqsckb min 2.0 ns max 10.0 data strobe edge to output data edge tdqsqb tdqsqb max 1.2 ns mode register parameters mode register write command period tmrw min 10 tck(avg) mode register read command period tmrr min 4 tck(avg) additional time after txp has expired until mrr command may be issued tmrri min trcd(min) ns
rev 1.1 / oct. 2013 67 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac timing parameters (4/5) parameter symbol min max lpddr3 1866 lpddr3 1600 lpddr3 1333 unit note core parameters 18 read latency rl min 14 12 10 tck(avg) write latency (set a) wl min 8 66 tck(avg) write latency (set b) wl min 11 98 tck(avg) active to active command period trc min tras+trpab (with all-bank precharge) tras+trppb (with per-bank precharge) ns cke min. pulse width during self-refresh (low pulse width during self-refresh) tckesr min max(15ns, 3nck) ns self refresh exit to next valid command delay txsr min max(trfc ab +10ns, 2nck) ns exit power down to next valid command delay txp min max(7.5ns, 3nck) ns cas to cas delay tccd min 4 tck(avg) internal read to precharge command delay trtp min max(7.5ns, 4nck) ns ras to cas delay trcd min max(18ns, 3nck) ns row precharge time (single bank) trppb min max(18ns ,3nck) ns row precharge time (all banks) - 8-bank trpab min max(21ns, 3nck) ns row active time tras min max(42ns, 3nck) ns max 70,000 write recovery time twr min max(15ns, 4nck) ns internal write to read command delay twtr min max(7.5ns, 4nck) ns active bank a to active bank b trrd min max(10ns, 2nck) ns four bank activate window tfaw min max(50ns, 8nck) ns minimum deep power down time tdpd min 500 us odt parameters asynchronous rtt turn-on dely from odt in- put todton min 1.75 ns max 3.5 asynchronous rtt turn-off delay from odt in- put todtoff min 1.75 ns max 3.5 automatic rtt turn-on delay after read data taodton max tdqsckmax + 1.4 * tdqsq- max + tck(avg,min) ps automatic rtt turn-off delay after read data taodtoff min tdqsckmin - 300 ps rtt disable delay from power down, self-re- fresh, and deep power down entry todtd min 12 ns rtt enable delay from power down and self re- fresh exit todte max 12 ns
rev 1.1 / oct. 2013 68 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ac timing parameters (5/5) parameter symbol min max lpddr3 1866 lpddr3 1600 lpddr3 1333 unit note ca training parameters first ca calibratino command after ca calibra- tion mode is programmed tcamrd min 20 tck(avg) first ca calibratino command after cke is low tcaent min 10 tck(avg) ca calibration exit command after cke is high tcaext min 10 tck(avg) cke low after ca calibration mode is pro- grammed tcackel min 10 tck(avg) cke high after the last ca calibration results are driven tcackeh min 10 tck(avg) data out delay after ca training calibration command is programmed tadr max 20 ns mrw ca exit command to dq tri-state tmrz min 3 ns ca calibration command to ca calibration com- mand delay tcacd min ru(tadr+2*tck) tck(avg) write leveling parameters dqs_t/dqs_c delay after write leveling mode is programmed twldqsen min 25 ns max - first dqs_t/dqs_c edge after write leveling mode is programmed twlmrd min 40 ns max - write leveling output delay twlo min 0 ns max 20 write leveling hold time twlh min 150 175 205 ps write leveling setup time twls min 150 175 205 ps mode register set command delay tmrd min max(14ns, 10nck) ns max - temperature de-rating 17 tdqsck de-rating tdqsck (derated) max 5620 ps core timings temperature de-rating trcd (derated) min trcd + 1.875 ns trc (derated) min trc + 1.875 ns tras (derated) min tras + 1.875 ns trp (derated) min trp + 1.875 ns trrd (derated) min trrd + 1.875 ns
rev 1.1 / oct. 2013 69 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. frequency values are for reference only. clock cycle time (tck) is used to dete rmine device capabilities. 2. all ac timings assume an input slew rate of 2 v/ns. 3. measured with 4v/ns differential ck_t/ck_c slew rate and nominal vix. 4. all timing and voltage measur ements are defined 'at the ball'. 5. read, write, and input setup and hold values are referenced to vref. 6. tdqsckds is the absolute value of the difference between any two tdqsck measurements (in a byte lane) within a contigu- ous sequence of bursts in a 160ns rolling window. tdqsckds is not tested and is guaranteed by design. temperature drift in the system is < 10 c/s. values do not include clock jitter. 7. tdqsckdm is the absolute value of the difference between any two tdqsck measurements (in a byte lane) within a 1.6 s rolling window. tdqsckdm is not tested and is guaranteed by design. temperature drif t in the system is < 10 c/s. values do not include clock jitter. 8. tdqsckdl is the absolute value of the difference between any two tdqsck measurements (in a byte lane) within a 32ms roll- ing window. tdqsckdl is not tested and is guaranteed by design . temperature drift in the system is < 10 c/s. values do not include clock jitter. 9. for low-to-high and high-to-lo w transitions, the timing reference is at the point when the signal crosses the transition threshold (vtt). thz and tlz transitions occur in the same access time (with respect to clock) as valid data transitions. these parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for trps t, thz(dqs) and thz(dq)), or begins driving (for trpre, tlz(dqs) , tlz(dq)). figure shows a method to calculate the point when device is no longer driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq ) by measuring the sign al at two different voltages. the actual voltage measurem ent points are not critic al as long as the calc ulation is consistent. 10. output transition timing figure. hsul_12 dr iver output reference load for timing and slew rate 11. the parameters tlz(dqs), tlz(dq), thz( dqs), and thz(dq) are defined as single-end ed. the timing parameters trpre and trpst are determined from the differential signal dqs/dqs#. 12. measured from the point when dqs_t/dqs_c begins driving the signal to the point when dqs_t/dqs_c begins driving the first rising strobe edge. 13. measured from the last falling strobe edge of dqs_t/dqs_c to the point when dqs_t/dqs_c finishes driving the signal. 14. cke input setup time is measured from cke reachi ng a high/low voltage leve l to ck_t/ck_c crossing. 15. cke input hold time is measured from ck_t/ck_c crossing to cke reaching a high/low voltage level. 16. input set-up/hold time for signal (ca[9:0], cs_n). 17. to ensure device operation before the device is configured, a number of ac boot-timing parame ters are defined in this table . boot parameter symbols have the letter b appended (for example, tck during boot is tckb). 18. the lpddr3 device will set some mode register default valu es upon receiving a reset (mrw) command as specified in ?mode register definition?. 19. the output skew parameters are measured with defa ult output impedance settings using the reference load. 20. the minimum tck column applies on ly when tck is greater than 6ns. thz(dqs), thz(dq) stop driving point = 2 x t1 - t2 vol + 2x x mv t1 t2 vol + x mv voh - x mv voh - 2x x mv tlz(dqs), tlz(dq) begin driving point = 2 x t1 - t2 vol vtt - y mv voh t2 t1 vtt - 2x y mv vtt + 2x y mv vtt + y mv vtt vtt y 2x y actual waveform x 2x x
rev 1.1 / oct. 2013 70 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) ca and cs_n setup, hold and derating for all input signals (ca and cs_n) the to tal tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) value to the ? tis and ? tih derating value respectively. example: tis (total setup time) = tis(base) + ? tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the la st crossing of vref(dc) and the first crossing of vih(ac)min. setup (t is) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the fi rst crossing of vil(ac)max. if the actual signal is always earlier than the nom- inal slew rate line between shaded `vref(dc) to ac region', use nominal slew rate for derating value. if the actual sig- nal is later than the nominal slew rate line anywhere betw een shaded `vref(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tih) nominal slew rate for a rising signal is defined as the slew rate betw een the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the firs t crossing of vref(dc). if the actual signal is alwa ys later than the nominal slew rate line between shaded `dc to vref(dc) region', use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere betwee n shaded `dc to vref(dc) regi on', the slew rate of a tan- gent line to the actual signal from the dc leve l to vref(dc) level is used for derating value. for a valid transition the input si gnal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total se tup time might be negative (i.e. a valid input signal will not have reached vih/ il(ac) at the time of the rising clock transition) a valid input signal is still required to co mplete the transition and reach vih/il(ac). for slew rates in between the values listed in table, th e derating values may obtain ed by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. table. ca setup and hold base-values note 1: ac/dc referenced for 2v/ns ca slew ra te and 4v/ns differential ck_t/ck_c slew rate. table. cs_n setup and hold base-values note 1: ac/dc referenced for 2v/ns cs_n slew ra te and 4v/ns differential ck_t/ck_c slew rate. unit [ps] lpddr3 1866 lpddr3 1600 lpddr3 1333 reference tis(base) - 75 100 vih/l(ac)=vref(dc)+/-150mv tis(base) 62.5 - - vih/l(ac)=vref(dc)+/-135mv tih(base) 80 100 125 vih/l(dc)=vref(dc)+/-100mv unit [ps] lpddr3 1866 lpddr3 1600 lpddr3 1333 reference tis(base) - 195 215 vih/l(ac)=vref(dc)+/-150mv tis(base) 162.5 - - vih/l(ac)=vref(dc)+/-135mv tih(base) 180 220 240 vih/l(dc)=vref(dc)+/-100mv
rev 1.1 / oct. 2013 71 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. derating values tis/tih - ac/dc based ac150 note 1: cell contents shaded in red are defined as ?not supported? table. derating values tis/tih - ac/dc based ac150 note 1: cell contents shaded in red are defined as ?not supported? table. required time t vac above vih(ac) {below vil( ac)} for valid transition ? tisca, ? tihca, ? tiscs, ? tihcs derating in [ps] ac/dc based ac150 threshold -> vih(ac)=vref(d c)+150mv, vil(ac)=vref(dc)-150mv dc100 threshold -> vih(dc)=vref(d c)+100mv, vil(dc)=vref(dc)-100mv 8.0 v/ns 7.0 v/ns 6.0 v/ns 5.0 v/ns 4.0 v/ns 3.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ca, cs_n slew rate v/ns 4.038253825382538253825 3.0 25 17 25 17 25 17 25 17 38 29 2.0 0000001313 1.5 -25 -17 -25 -17 -12 -4 ? tisca, ? tihca, ? tiscs, ? tihcs derating in [ps] ac/dc based ac150 threshold -> vih(ac)=vref(d c)+150mv, vil(ac)=vref(dc)-150mv dc100 threshold -> vih(dc)=vref(d c)+100mv, vil(dc)=vref(dc)-100mv 8.0 v/ns 7.0 v/ns 6.0 v/ns 5.0 v/ns 4.0 v/ns 3.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ca, cs_n slew rate v/ns 4.034253425342534253425 3.0 23 17 23 17 23 17 23 17 34 29 2.0 0000001113 1.5 -23 -17 -23 -17 -12 -4 slew rate [v/ns] t vac [ps] @135mv t vac [ps] @150mv t vac [ps] @150mv 1866mbps 1600mbps 1333mbps min max min max min max > 4.0 40 - 48 - 58 - 4.0 40 - 48 - 58 - 3.5 39 - 46 - 56 - 3.0 36 - 43 - 53 - 2.5 33 - 40 - 50 - 2.0 29 - 35 - 45 - 1.5 21 - 27 - 37 - <1.5 21 - 27 - 37 -
rev 1.1 / oct. 2013 72 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illustration of nominal slew rate and t vac for setup time t is for ca and cs_n with respect to clock v ssca setup slew rate setup slew rate rising signal ? tf ? tr v ref(dc) - v il(ac) max ? tf = v ih(ac) min - v ref(dc) ? tr = v ddca v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tih tis ck_t ck_c tih tis falling signal
rev 1.1 / oct. 2013 73 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illustration of nominal slew rate for hold time tih for ca and cs_n with respect to clock v ssca hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - v il(dc) max ? tr = v ih(dc) min - v ref(dc) ? tf = v ddca v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tih tis ck_t ck_c tih tis
rev 1.1 / oct. 2013 74 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illustration of tangent line for setup time t is for ca and cs_n with respect to clock v ssca tih setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line[ v ref(dc) - v il(ac) max] ? tf = tangent line[v ih(ac) min - v ref(dc) ] ? tr = v ddca v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac ck_t ck_c tih tis
rev 1.1 / oct. 2013 75 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illustration of tangent line for hold time t ih for ca and cs_n with respect to clock v ssca hold slew rate ? tf ? tr tangent line [v ih(dc) min - v ref(dc) ] ? tf = v ddca v ih(ac) min v ih(dc min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] ? tr = rising signal tih tis ck_t ck_c tih tis
rev 1.1 / oct. 2013 76 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) data setup, hold an d slew rate derating for all input signals (dq, dm) the total tds (setup time) and tdh (hold time) required is ca lculated by adding the data sheet tds(base) and tdh(base) value to the ? tds and ? tdh derating value respectively. example: tds (total setup time) = tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the la st crossing of vref(dc) and the first crossing of vih(ac)min. setup (t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the fi rst crossing of vil(ac)max. if the actual signal is always earlier than the nom- inal slew rate line between shaded `vref(dc) to ac region', use nominal slew rate for derating value. if the actual sig- nal is later than the nominal slew rate line anywhere betw een shaded `vref(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling sign al is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref (dc). if the actual signal is always later than the nominal slew rate line between shaded `dc level to vref(dc) region', use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to vref(dc) region', the slew rate of a tangent line to the actual signal from the dc le vel to vref(dc) level is used for derating value. for a valid transition the input si gnal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total se tup time might be negative (i.e. a valid input signal will not have reached vih/ il(ac) at the time of the rising clock transition) a valid input signal is still required to co mplete the transition and reach vih/il(ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. table. data setup and hold base-values note 1: ac/dc referenced for 1v/ns dq, dm slew rate and 2v/ns differential dqs_t-dqs_c slew rate. unit [ps] lpddr3 1866 lpddr3 1600 lpddr3 1333 reference tds(base) - 75 100 vih/l(ac)=vref(dc)+/-150mv tds(base) 62.5 - - vih/l(ac)=vref(dc)+/-135mv tdh(base) 80 100 125 vih/l(dc)=vref(dc)+/-100mv
rev 1.1 / oct. 2013 77 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. derating values lpddr3 tds/tdh - ac/dc based ac150 note 1: cell contents shaded in red are defined as ?not supported? table. derating values lpddr3 tds/tdh - ac/dc based ac135 note 1: cell contents shaded in red are defined as ?not supported? table. required time t vac above vih(ac) {below vil( ac)} for valid transition ? tds, ? tdh derating in [ps] ac/dc based ac150 threshold -> vih(ac)=vref(dc)+150mv, vil(ac)=vref(dc)-150mv dc100 threshold -> vih(dc)=vref(dc)+100mv, vil(dc)=vref(dc)-100mv 8.0 v/ns 7.0 v/ns 6.0 v/ns 5.0 v/ns 4.0 v/ns 3.0 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq,dm slew rate v/ns 4.038253825382538253825 3.0 25 17 25 17 25 17 25 17 38 29 2.0 0000001313 1.5 -25 -17 -25 -17 -12 -4 ? tds, ? tdh derating in [ps] ac/dc based ac150 threshold -> vih(ac)=vref(dc)+150mv, vil(ac)=vref(dc)-150mv dc100 threshold -> vih(dc)=vref(dc)+100mv, vil(dc)=vref(dc)-100mv 8.0 v/ns 7.0 v/ns 6.0 v/ns 5.0 v/ns 4.0 v/ns 3.0 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq,dm slew rate v/ns 4.034253425342534253425 3.0 23 17 23 17 23 17 23 17 34 29 2.0 0000001113 1.5 -23 -17 -23 -17 -12 -4 slew rate [v/ns] t vac [ps] @135mv t vac [ps] @150mv t vac [ps] @150mv 1866mbps 1600mbps 1333mbps min max min max min max > 4.0 40 - 48 - 58 - 4.0 40 - 48 - 58 - 3.5 39 - 46 - 56 - 3.0 36 - 43 - 53 - 2.5 33 - 40 - 50 - 2.0 29 - 35 - 45 - 1.5 21 - 27 - 37 - <1.5 21 - 27 - 37 -
rev 1.1 / oct. 2013 78 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illustration of nominal slew rate and t vac for setup time t ds for dq with re spect to strobe v ssq setup slew rate setup slew rate rising signal falling signal ? tf ? tr v ref(dc) - v il(ac) max ? tf = v ih(ac) min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs_t dqs_c tdh tds
rev 1.1 / oct. 2013 79 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illustration of nominal slew rate for hold time t dh for dq with respect to strobe v ssq hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - v il(dc) max ? tr = v ih(dc) min - v ref(dc) ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(dc) max nominal slew rate nominal slew rate region dc to v ref region tdh tds dqs_t dqs_c tdh tds dc to v ref
rev 1.1 / oct. 2013 80 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illu stration of tangent li ne for setup time t ds for dq with re spect to strobe v ssq tdh setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line[ v ref(dc) - v il(ac) max] ? tf = tangent line[v ih(ac) min - v ref(dc) ] ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs_t dqs_c tdh tds
rev 1.1 / oct. 2013 81 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. illu stration of tangent li ne for hold time t dh for dq with respect to strobe v ssq hold slew rate ? tf ? tr tangent line [v ih(dc) min - v ref(dc) ] ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] ? tr = rising signal tdh tds dqs_t dqs_c tdh tds
rev 1.1 / oct. 2013 82 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) clock specification the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max values may result in malfunction of the lpddr3 device. definition for tck(avg) and nck tck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. unit `tck(avg)' represents the actual cl ock average tck(avg) of the input clock under operation. unit `nck' represents one clock cycle of the input clock, counting the actual clock edges. tck(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specifications are met. definition for tck(abs) tck(abs) is defined as the absolute clock period, as measur ed from one rising edge to the next consecutive rising edge. tck(abs) is not subject to production test. definition for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
rev 1.1 / oct. 2013 83 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) definition for tjit(per) tjit(per) is the single period jitter defined as th e largest deviation of any signal tck from tck(avg). tjit(per) = min/max of {tck i - tck(avg) where i = 1 to 200}. ? tjit(per),act is the actual clock jitter for a given system.? tjit(per),allowed is the specifie d allowed clock period jitter.? tjit(per) is not subjec t to production test. definition for tjit(cc) tjit(cc) is defined as the absolu te difference in clock period be tween two consecutive clock cycles. tjit(cc) = max of |{tck i+1 - tck i }|. ? tjit(cc) defines the cycle to cycle jitter.? tjit(cc) is not subject to production test. definition for terr(nper) terr(nper) is defined as the cumulative error acro ss n multiple consecutive cycles from tck(avg). terr(nper),act is the actual clock jitter over n cycles for a given system.? terr(nper),allowed is the specified allowe d clock period jitter over n cycles.? terr(nper) is not subject to production test. terr(nper),min can be calculated by the formula shown below: terr(nper),max can be caculate d by the formula shown below: using these equations, terr(nper) tables can be generated for each tjit(per),act value
rev 1.1 / oct. 2013 84 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) definition for duty cycle jitter tjit(duty) tjit(duty) is defined with absolute and average specification of tch / tcl. tjit(duty),min can be caculate d by the formula shown below: tjit(duty),max can be caculated by the formula shown below: definition for tck(abs), tch(abs) and tcl(abs) these parameters are specified per their average values, ho wever it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. note: 1. tck(avg),min is expressed in ps for this table 2. tjit(duty),min is a negative value parameter symbol min unit absolute clock period tck(abs) tc k(avg),min + tjit(per),min ps absolute clock high pulse widt h tch(abs) tch(avg),min + tjit(dut y),min / tck(av g)min tck(avg) absolute clock low pulse width tcl(abs) tcl(avg ),min + tjit(duty),min / tck(avg)min tck(avg)
rev 1.1 / oct. 2013 85 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) period clock jitter lpddr3 devices can tolerate some clock period jitter withou t core timing parameter de-rating. this section describes device timing requirements in the presence of clock period ji tter (tjit(per)) in excess of th e values found in ?ac timing table? and how to determine cycle time de-rating and clock cycle de-rating. clock period jitter effects on core timing parameters (trcd, trp, trtp, twr, twra, twtr, trc, tras, trrd, tfaw ) core timing parameters extend across multiple clock cycl es. period clock jitter will impact these parameters when measured in numbers of clock cycles. when the device is operated with clock ji tter within the specification limits, the lpddr3 device is characterized and verified to support tnparam = ru{tparam / tck(avg)}. when the device is operated with clock jitter outside specification limits, the numb er of clocks or tck(avg) may need to be increased based on the values for each core timing parameter. cycle time de-rating for core timing parameters for a given number of clocks (tnparam), for each core timi ng parameter, average clock period (tck(avg)) and actual cumulative period error (terr(tnparam),act) in excess of the allowed cumulative period error (terr(tnparam),allowed), the equation be low calculates the amount of cycle time de-rating (in ns) required if the equation results in a positive value for a core timing parameter (tcore). a cycle time derating analysis should be conducted for each core timing paramete r. the amount of cycle time derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter. clock cycle de-rating for core timing parameters for a given number of clocks (tnparam) for each core timing parameter, clock cycle de-rating should be specified with amount of period jitter (tjit(per)). for a given number of clocks (tnparam), for each core timi ng parameter, average clock period (tck(avg)) and actual cumulative period error (terr(tnparam),act) in excess of the allowed cumulative period error (terr(tnparam),allowed), the eq uation below calculates the clock cycle dera ting (in clocks) requir ed if the equation results in a positive value for a core timing parameter (tcore). a clock cycle de-rating analysis should be conducted for each core timing parameter. clock jitter effects on comm and/address timing parameters (tis, tih, tiscke, tihcke, tisb, tihb, tisckeb, tihckeb) these parameters are measured from a command/address sign al (cke, cs, ca0 - ca9) transition edge to its respec- tive clock signal (ck_t/ck_c) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met.
rev 1.1 / oct. 2013 86 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) clock jitter effects on read timing parameters trpre when the device is operated with input clock jitter, tr pre needs to be de-rated by the actual period jitter (tjit(per),act,max) of the input clock in excess of the allowe d period jitter (tji t(per),allowed,max). output de-ratings are relative to the input clock. for example, if the measured jitter into a lpddr3-1600 device ha s tck(avg) = 1250 ps, tjit(per),act,min = -92 ps and tjit(per),act,max = + 134 ps, then, trpre,min,derated = 0.9 - (tjit(per),act ,max - tjit(per),allowed,max)/tck(avg) = 0.9 - (134 - 100)/1250= .8728 tck(avg) tlz(dq), thz(dq), tdqsck, tlz(dqs), thz(dqs) these parameters are measured from a specific clock edge to a data signal (dmn, dqm: n=0,1,2,3, m=0-31) transi- tion and will be met with respect to th at clock edge. therefore, they are not af fected by the amount of clock jitter applied (i.e. tjit(per)). tqsh, tqsl these parameters are affected by duty cycle jitter whic h is represented by tch(abs)min and tcl(abs)min. these parameters determine absolute data-valid window (dvw) at the lpddr3 device pin. absolute min dvw @ lpddr3 device pin = min{ ( tqsh(abs)min ? tdqsqmax) , ( tqsl(abs)min ? tdqsqmax ) } this minimum dvw shall be met at the targ et frequency regardless of clock jitter. trpst trpst is affected by duty cycle jitter which is represente d by tcl(abs). therefore trpst( abs)min can be specified by tcl(abs)min. trpst(abs)min = tcl(abs)min ? 0.05 = tqsl(abs)min
rev 1.1 / oct. 2013 87 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) clock jitter effects on write timing parameters tds, tdh these parameters are measured from a data signal (dmn, dq m.: n=0,1,2,3. m=0 ?31) transition edge to its respec- tive data strobe signal (dqsn_t, dqsn _c : n=0,1,2,3) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), as th e setup and hold are relative to the data strobe signal crossing that latches the data. regardless of clock jitter values, these values shall be met. tdss, tdsh these parameters are measured from a data strobe signal (dqsx_t, dqsx_c) crossing to its respective clock signal (ck_t/ck_c) crossing. the spec values are not affected by th e amount of clock jitter appl ied (i.e. tjit(per), as the setup and hold of the data strobes are re lative to the corresponding clock signal crossing. regardless of clock jitter val- ues, these values shall be met. tdqss this parameter is measured from a data strobe signal (d qsx_t, dqsx_c) crossing to the subsequent clock signal (ck_t/ck_c) crossing. when the device is operated with inpu t clock jitter, this parameter needs to be de-rated by the actual period jitter tjit(per),act of the input clock in excess of the allo wed period jitter tjit(per),allowed. tdqss(min,derated) can be caculated by the formula shown below: tdqss(max,derated) can be cacula ted by the formula shown below: for example, if the measured jitter into a lpddr3-1600 device has tck(avg)= 1250 ps, tjit(per),act,min= -93 ps and tjit(per),act,max= + 134 ps, then tdqss,(min,derated) = 0.75 - (tjit(per),act,min - tjit(per),a llowed,min)/tck(avg) = 0.75 - (-93 + 100)/1250 = 0.7444 tck(avg) and tdqss,(max,derated) = 1.25 - (tjit(per),act,max - tjit(per),a llowed,max)/tck(avg) = 1.25 - (134 - 100)/1250 = 1.2228 tck(avg)
rev 1.1 / oct. 2013 88 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) refresh requirements lpddr3 read and write latencies note: 1. rl=3/wl=1 setting is an optional feature. refer to mr0 op<7>. 2. write latency (set b) support is an optional fe ature. refer to mr0 op<6>. density symbol 4gb 8gb 16gb unit number of banks 8 - refresh window tcase <= 85?c trefw 32 ms refresh window 1/2-rate refresh trefw 16 ms refresh window 1/4-rate refresh trefw 8 ms required number of refresh commands (min) r8,192- average time between refresh commands (for reference only) tcase <= 85?c refab trefi 3.9 us refpb trefipb 0.4875 0.4875 0.4875 us refresh cycle time trfcab 130 210 tbd ns per bank refresh cycle time trfcpb 60 90 tbd ns burst refresh window = 4 x 8 x trfcab trefbw 4.16 6.72 tbd us parameter lpddr3 unit 333 800 1066 1200 1333 1466 1600 max. clock frequency 166 400 533 600 667 733 800 nhz max. data rate 333 800 1066 1200 1333 1466 1600 mt/s average clock period 6 2.5 1.875 1.67 1.5 1.36 1.25 ns read latency 3 6 8 9 10 11 12 tck(avg) write latency (set a)1345666tck(avg) write latency (set b)1345899tck(avg)
rev 1.1 / oct. 2013 89 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) command definitions activate command the activate command is issued by hold ing cs_n low, ca0 low, and ca1 high at the rising edge of the clock. the bank addresses ba0 to ba2 are used to select the desired bank. row addresses are used to determine which row to activate in the selected bank. the activate command must be applied before any read or write operation can be executed. the device can accept a read or write command at trcd after the activate command is issued. after a bank has been activated it must be precharged before an other activate command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the mi nimum time interval between successive activate commands to the same bank is determin ed by the ras cycle time of the device (trc). the mini- mum time interval between activate commands to different banks is trrd. note: 1. a precharge-all command uses trpab timing, while a single -bank precharge command uses trppb timing. in this figure, trp is used to denote either an all-ba nk precharge or a single-bank precharge. figure. activate command certain restrictions on operation of the 8-bank lpddr3 devices must be observed. th ere are two rules: one rule restricts the number of sequential activate commands that can be issued; the other provides more time for ras pre- charge for a precharge all command. the rules are as follows: ? 8 bank device sequential bank activation restriction: no more than 4 banks may be activated (or refreshed, in the case of refpb) in a rolling tfaw window. the number of clocks in a tfaw period is dependent upon the clock fre- quency, which may vary. if the clock freque ncy is not changed over this period, co nverting clocks is done by dividing tfaw[ns] by tck[ns], and rounding up to the next integer value. as an exam ple of the rolling window, if ru(tfaw/ tck) is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands can be issued at or between clock n + 1 and n + 9. refpb also counts as bank activation for purposes of tfaw. if the clock frequency is changed during the tf aw period, the rolling tfaw window ma y be calculated in clock cycles by adding up the time spent in each clock period. the tfaw requirement is met when th e previous n clock cycles exceeds the tfaw time. ? 8 bank device precharge all allowance: trp for a prechr ge all command must equal tr pab, which is greater than trppb. nop nop nop read precharge activate activate bank a row bank a bank a trcd trrd trp trc col bank a bank b activate ck_t/ck_c ca0-9 [cmd] tras addr row addr row addr addr col addr row addr row addr read begins row addr
rev 1.1 / oct. 2013 90 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. tfaw timing command input setup and hold timing note: 1. setup and hold conditions al so apply to the cke pin. see section related to power down for timing diagrams related to the cke pin. figure. command input setup and hold timing nop tn tn+1 tm tm+1 tx tx+1 ty ty+1 tz ck_t/ act nop nop nop nop ca0-9 [cmd] trrd bank a act act act act act tz+1 bank b bank c bank d bank e ck_c trrd trrd tfaw command command ca rise ca fall ca rise ca fall ca ca rise ca fall ca rise t0 t1 t2 t3 tiscs tihcs tiscs tihcs tisca tihca ck_t/ck_c cs_n ca0-9 [cmd] vil(ac) vil(dc) vih(dc) tisca tihca nop nop ca fall vih(ac) high or low (but a defined logic level)
rev 1.1 / oct. 2013 91 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) cke input setup and hold timing note: 1. after cke is registered low, cke signal level shall be maintained below vilcke for tcke specification (low pulse width). 2. after cke is registered high, cke signal level shal l be maintained above vihcke for tcke specification (high pulse width). figure. cke input setup and hold timing read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting cs_n low, ca0 high, and ca1 low at the rising edge of the clock. ca2 must also be defined at this time to determine whether the access cycle is a read operation (ca2 high) or a write operation (ca2 low). the lpddr3 sdram provides a fast column access operation. a single read or write command will initiate a burst read or write operation on successive cloc k cycles. burst interrupts are not allowed. burst read command the burst read command is initiated with cs_n low, ca0 high, ca1 low, and ca2 high at the rising edge of the clock. the command address bus inputs ca5r?ca6r and ca1f?c a9f determine the starting column address for the burst. the read latency (rl) is defined from the rising edge of the clock on which the read command is issued to the rising edge of the clock from which the tdqsck delay is measured . the first valid data is available rl tck + tdqsck + tdqsq after the rising edge of the clock when the read command is issued . the data strobe output is driven low trpre before the first valid rising strobe edge. the first bit of the burst is synchronized with the first rising edge of the data strobe. each subsequent data-out appears on each dq pin, edge-aligned with the data strobe. the rl is pro- grammed in the mode registers. pin timi ngs for the data strobe are measured re lative to the crosspoint of dqs_t and its complement, dqs_c. t0 t1 tx tx+1 tihcke ck_t/ck_c cke vilcke vihcke high or low (but a defined logic level) tihcke tiscke tiscke vilcke vihcke
rev 1.1 / oct. 2013 92 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. read output timing note: 1. tdqsck can span multiple clock periods. 2. an effective burst length of 8 is shown. figure. burst read : rl=12, bl=8, tdqsck>tck figure. burst read : rl=12, bl=8, tdqsck rev 1.1 / oct. 2013 93 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. lpddr3 : tdqsckdl timing note: 1. tdqsckdlmax is defined as the maximu m of abs(tdqsckn - tdqsckm) for any {tdqsckn ,tdqsckm} pair within any 32ms rolling window. figure. lpddr3 : tdqsckdm timing note: 1. tdqsckdmmax is defined as the maxi mum of abs(tdqsckn - tdqsckm) for any {tdqsckn ,tdqsckm} pair within any 1.6us rolling window. figure. lpddr3 : tdqsckds timing note: 1. tdqsckdsmax is defined as the maxi mum of abs(tdqsckn - tdqsckm) for any {tdqsckn ,tdqsckm} pair within any 160ns rolling window. nop tn tn+1 tn+2 tn+5 tn+6 tn+7 tn+8 tn+9 ck_t/ck_c read nop nop nop nop nop nop nop dqs ca0-9 [cmd] tdqsckn dqs_t/dqs_c bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 nop tm tm+1 tm+2 tm+5 tm+6 tm+7 tm+8 tm+9 read nop nop nop nop nop nop nop tdqsckm bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 rl = 6 rl = 6 32ms maximum tdqsckdl = | tdqsckn - tdqsckm| nop tn tn+1 tn+2 tn+5 tn+6 tn+7 tn+8 tn+9 ck_t/ck_c read nop nop nop nop nop nop nop dqs ca0-9 [cmd] tdqsckn dqs_t/dqs_c bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 nop tm tm+1 tm+2 tm+5 tm+6 tm+7 tm+8 tm+9 read nop nop nop nop nop nop nop tdqsckm bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 rl = 6 rl = 6 1.6us maximum tdqsckdl = | tdqsckn - tdqsckm| nop tn tn+1 tn+2 tn+5 tn+6 tn+7 tn+8 tn+9 ck_t/ck_c read nop nop nop nop nop nop nop dqs ca0-9 [cmd] tdqsckn dqs_t/dqs_c bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 nop tm tm+1 tm+2 tm+5 tm+6 tm+7 tm+8 tm+9 read nop nop nop nop nop nop nop tdqsckm bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 rl = 6 rl = 6 160ns maximum tdqsckdl = | tdqsckn - tdqsckm|
rev 1.1 / oct. 2013 94 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. burst read followed by burst write: rl=12, wl=6, bl=8 the minimum time from the burst read command to the bu rst write command is defined by the read latency (rl) and the burst length (bl). minimum re ad-to-write latency is rl + ru(tdqsc k(max)/tck) + bl/2 + 1 - wl clock cycles. figure. seamless burst read: rl = 6, bl = 8, tccd = 4 the seamless burst read operation is supported by enabling a read command at every fourth clock cycle for bl = 8 operation. this operation is supported as long as the bank s are activated, whether the accesses read the same or dif- ferent banks. nop t0 t1 t2 t12 ta-1 ta ta+1 ta+2 ck_t/ck_c read nop nop nop nop nop nop dqs ca0-9 [cmd] tdqsck dout dout dout dout rl = 12 dqs_t/dqs_c bank a col dout dout dout dout addr col addr a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 ta +3 ta + 4 nop ta + 5 nop nop bl/2 wl = 6 tdqssmin din a 0 din a 1 din a 2 write bank a col addr col addr nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 ck_t/ck_c read nop nop nop nop nop dqs ca0-9 [cmd] dout dout dout dout rl = 6 dqs_t/dqs_c bank a col dout dout dout dout addr a col addr a a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 t9 t10 nop t11 nop t12 nop nop t13 nop t14 nop t15 read bank a col addr b col addr b read bank a col addr c col addr c read bank a col addr d col addr d tccd = 4 tccd = 4 dout dout dout dout dout dout dout dout b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dout dout c 0 c 1
rev 1.1 / oct. 2013 95 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) burst write operation the burst write command is initiated wi th cs_n low, ca0 high, ca1 low, and ca2 low at the rising edge of the clock. the command address bus inputs, ca5r?ca6r and ca1f ?ca9f, determine the starting column address for the burst. write latency (wl) is defined from the rising edge of the clock on which the writ e command is issued to the rising edge of the clock from which the tdqss delay is me asured. the first valid data must be driven wl tck + tdqss from the rising edge of the clock from which the wr ite command is issued. the data strobe signal (dqs) must be driven for time twpre prior to data input. the burst cycle data bits must be applied to the dq pins tds prior to the associated edge of the dqs and held valid until tdh after th at edge. burst data is sampled on successive edges of the dqs until the 8-bit burst length is co mpleted. after a burst write operation, twr must be satisfied before a pre- charge command to the same bank can be issued. pin input timings are measured relative to the crosspoint of dqs_t and its complement, dqs_c. figure. data input (write) timing figure. burst write dqs_t/dqs_c dq dm din din din din tdqsh tdqsl twpst tdh tds tds vih(ac) twpre vil(ac) vih(ac) vil(ac) tdqsl vih(ac) vil(ac) tdh tdh vih(ac) vil(ac) tds vih(ac) vil(ac) vih(ac) vil(ac) dm dm dm dm nop t0 ta ta+1 ... ta+7 tx tx+1 ty ty+1 ck_t/ck_c write nop nop dqs ca0-9 [cmd] bank a col din din din din bank a bank a row nop precharge activate dqs_t/dqs_c dqs din din din din dqs_t/dqs_c case1: with tdqss (max) tdqss max ttd tdss wl = a wl = a tdqss min tdsh tdsh trp case2: with tdqss (min) addr col addr addr row addr a0 a1 a6 a7 a0 a1 a2 a7 nop nop twr completion of burst write
rev 1.1 / oct. 2013 96 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) twpre calculation the method for calculating twpre is shown in the following figure. figure. method for caculating twpre transitions and endpoints twpst calculation the method for calculating twpst is shown in the following figure. figure. method for caculating twpre transitions and endpoints ck_t twpre begins vtt t1 ck_c dqs_t - dqs_c 0v t2 twpre ends resulting differential signal relevant for twpre specification ck_t twpst begins vtt t1 ck_c dqs_t - dqs_c 0v t2 twpst ends resulting differential signal relevant for twpst specification
rev 1.1 / oct. 2013 97 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. the minimum number of clock cycles from the burst writ e command to the burst read command for any bank is [wl + 1 + bl/2 + ru(twtr/tck)]. 2. twtr starts at the rising edge of the clock after the last valid input datum. figure. burst write followed by burst read note: 1. the seamless burst write operation is su pported by enabling a write command every four clocks for bl = 8 operation. this operation is supported for any activated bank. figure. seamless burst write nop t0 tx tx+1 tx+2 tx+5 tx+6 tx+7 tx+8 tx+9 ck_t/ck_c write nop nop nop nop nop nop dqs ca0-9 [cmd] din din din din wl = x dqs_t/dqs_c bank n read bank m col rl twtr addr a col addr a col addr b col addr b a 0 a 1 a 2 a 7 nop t0 t1 t2 t3 t4 t5 t6 t7 ck_t/ck_c write nop nop nop nop dqs ca0-9 [cmd] din din din din dqs_t/dqs_c bank m col din din din din wl= 4 addr a col addr a a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 t8 t9 nop t10 t11 nop nop t12 t13 nop write bank n col addr b col addr b nop write bank n col addr c col addr c write bank n col addr d col addr d din din din din din din din din b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 din din c 0 c 1 tccd=4
rev 1.1 / oct. 2013 98 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) write data mask one write data mask (dm) pin for each data byte (dq) is supported, consistent with th e implementation on lpddr3 sdram. each dm can mask its respective dq for any given cycle of the burst. data mask timings match data bit tim- ing, but are inputs only. inte rnal data-mask loading is iden tical to data-bit lo ading to ensure matched system timing. note. 1. for the data mask function, bl=8 is shown; the second data bit is masked. tds tdh tds tdh dq dqs_t/dqs_c dm figure. data mask timing vil(ac) vih(ac) vil(ac) vih(ac) vil(dc) vih(dc) vil(dc) vih(dc) ck_t/ck_c write dq [cmd] dq dm wl tdqssmin tdqssmax twr case 1: min tdqss case 2: max tdqss dqs_t/dqs_c dm dqs_t/dqs_c 01 23 twtr 4 56 7 01 23 4 56 7
rev 1.1 / oct. 2013 99 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) precharge the precharge command is used to precharge or close a bank that has been activated. the precharge command is initiated with cs_n low, ca0 high, ca1 high, ca2 low, and ca3 high at the rising edge of the clock. the pre- charge command can be used to precharge each bank independently or all banks simultaneously. the ab flag and the bank address bits ba0, ba1, and ba2 are used to dete rmine which bank(s) to precha rge. the precharged bank(s) will be available for subsequent row access trpab after an all-bank precharge command is issued, or trppb after a single-bank precharge command is issued. to ensure that lpddr3 devices can m eet the instantaneous current demand re quired to operate, the row-precharge time for an all-bank precharge (trpab) will be longer than the row precharge time for a single-bank precharge (trppb). table. bank selection for precharge by address bits ab (ca4r) ba2 (ca9r) ba1 (ca8r) ba0 (ca7r) precharged bank(s) 8-bank device 0000 bank 0 only 0001 bank 1 only 0010 bank 2 only 0011 bank 3 only 0100 bank 4 only 0101 bank 5 only 0110 bank 6 only 0111 bank 7 only 1 don?t care don?t care don?t care all banks
rev 1.1 / oct. 2013 100 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) burst read operation followed by precharge for the earliest possible precharge, the precharge comma nd can be issued bl/2 clock cycles after a read com- mand. a new bank activate command can be issued to the same bank after the row precharge time (trp) has elapsed. a precharge command cannot be issued until af ter tras is satisfied. the minimum read-to-precharge time must also satisfy a minimum analog ti me from the rising clock edge that init iates the last 8-bit prefetch of a read command. trtp begins bl/2 - 4 cloc k cycles after the read command. figure. burst read followed by precharge t0 t1 tx tx+1 tx+2 tx+3 tx+4 tx+5 nop nop nop nop ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c dqs nop bank m c ol read c ol precharge rl bank m bank m row row activate trtp t rp dout a 0 dout a 1 dout a 2 dout a 3 dout a 4 dout a 5 dout a 6 dout a 7 addr a addr a addr addr nop
rev 1.1 / oct. 2013 101 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) burst write followed by precharge for write cycles, a write recovery time (twr) must be pr ovided before a precharge co mmand can be issued. this delay is referenced from the last valid burst input data to the completion of the bu rst write. precharge command must not be issued prior to the twr delay. lpddr3 devices write data to the array in prefetch multiples(prefetch = 8). an internal write operation can only begin after a prefetch group has been completely latched, so twr starts at prefetch boundaries. the minimum write- to-precharge time for commands to the same bank is wl + bl/2 + 1 + ru(twr/tck) clock cycles. figure. burst write followed by precharge t0 tx tx+1 tx+4 tx+5 ty tz tz+1 nop nop ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c dqs nop bank a c ol write c ol precharge wl bank a row row t dqssmax ? t rp bank a nop case 1: with t dqss (max) completion of burst write wl case 2: with t dqss (min) dqs_t/dqs_c dqs t dqssmin din a 0 din a 1 din a 6 din a 7 din a 0 din a 5 din a 6 din a 7 activate t wr nop t wr ty+1 nop addr addr addr addr
rev 1.1 / oct. 2013 102 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) auto precharge operation before a new row can be opened in an active bank, the ac tive bank must be precharged using either the precharge command or the auto precharge function. when a read or a write command is issued to the device, the ap bit (ca0f) can be set to enable the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if ap is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst. if ap is high when the read or write command is issued , the auto precharge function is engaged. this feature enables the precharge operation to be partially or comple tely hidden during burst read cycles (dependent upon read or write latency) thus improving system performance for random data access. burst read with auto precharge if ap (ca0f) is high when a read command is issued, th e read with auto-precharge function is engaged. lpddr3 devices start an auto-precharge operation on the rising e dge of the clock bl/2 or bl/2 - 2 4+ ru(trtp/tck) clock cycles later than the read with auto precharge command, whichever is greate r. for lpddr3 auto-precharge calcula- tions see the table in the next page. fo llowing an auto-precharge operation, an activate command can be issued to the same bank if the following two co nditions are satisfied simultaneously: a) the ras precharge time (trp) has been satisfied from the clock at which the auto- precharge begins. b) the ras cycle time (trc) from the prev ious bank activation has been satisfied. figure. burst read with auto-precharge t0 t1 tx tx+1 tx+2 tx+3 tx+4 tx+5 nop nop nop ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c dqs nop bank m c ol read c ol rl >= t rppb nop nop t rtp dout a 0 dout a 1 dout a 2 dout a 3 addr a addr a dout a 4 dout a 5 dout a 6 dout a 7 bank m row row activate addr addr nop
rev 1.1 / oct. 2013 103 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) burst write with auto precharge if ap (ca0f) is high when a write command is issued, the write with auto precharg e function is engaged. the device starts an auto precharge on the rising edge twr cy cles after the completion of the burst write. following a write with auto precharge, an activate command can be i ssued to the same bank if the following two conditions are met: the ras precharge time (trp) has been satisfied fr om the clock at which the auto- precharge begins. the ras cycle time (trc) from the previo us bank activation has been satisfied. figure. burst write with auto precharge t0 tx tx+1 ... tx+5 ty tz tz+1 nop nop nop ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c dqs nop bank a c ol write c ol wl bank a row row activate nop t wr nop din a 0 din a 1 din a 6 din a 7 nop addr addr addr addr >= t rppb ty+1
rev 1.1 / oct. 2013 104 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. precharge and auto precharge clarification from command to command minimum delay between from command to to command unit notes read precharge (to same bank as read) bl/2 + max(4, ru (trtp/tck)) - 4 clk 1 precharge all bl/2 + max(4, ru (trtp/tck)) - 4 clk 1 read w/ ap precharge (to same bank as read w/ ap) bl/2 + max(4, ru (trtp/tck)) - 4 clk 1 precharge all bl/2 + max(4, ru (trtp/tck)) - 4 clk 1 activate (to same bank as read w/ ap) bl/2 + max(4, ru (trtp/tck)) - 4 + ru(trppb/tck) clk 1 write or write w/ap (same bank) illegal clk 3 write or write w/ap (different bank) rl + bl/2 + ru(tdqsckmax/tck) -wl + 1 clk 3 read or read w/ap (same bank) illegal clk 3 read or read w/ap (different bank) bl/2 clk 3 write precharge (to same bank as write) wl + bl/2 + ru (twr/tck) + 1 clk 1 precharge all wl + bl/2 + ru (twr/tck) + 1 clk 1 write w/ ap precharge (to same bank as write w/ ap) wl + bl/2 + ru (twr/tck) + 1 clk 1 precharge all wl + bl/2 + ru (twr/tck) + 1 clk 1 activate (to same bank as write w/ ap) wl + bl/2 + ru (twr/tck) + 1 + ru(trppb/tck) clk 1 write or write w/ap (same bank) illegal clk 3 write or write w/ap (different bank) bl/2 clk 3 read or read w/ap (same bank) illegal clk 3 read or read w/ap (different bank) wl + bl/2 + ru(twtr/tck) + 1 clk 3 precharge precharge (to same bank as precharge) 1 clk 1 precharge all 1 clk 1 precharge all precharge 1 clk 1 precharge all 1 clk 1 note: 1. for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or pre - charge all, issued to that bank. the prec harge period is satisfied after trp dependin g on the latest precha rge command issued t o that bank. 2. any command issued during the minimum delay time as specified in table above is illegal. 3. after read with ap, seamless read oper ations to different banks are supported. after write with ap, seamless write operation s to different banks are supported. read w/ap and wr ite w/ap may not be interrupted or truncated.
rev 1.1 / oct. 2013 105 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) refresh command the refresh command is initiated with cs_n low, ca0 low, ca1 low, and ca2 high at the rising edge of the clock. per-bank refresh is initiated with ca3 low at the rising e dge of the clock. all-bank re fresh is initiated with ca3 high at the rising edge of the clock. a per-bank refresh command (refpb) performs a per-bank refresh operation to the bank scheduled by the bank counter in the memory device. the bank sequence for per-bank refresh is fixed to be a sequential round-robin: 0-1- 2-3-4-5-6-7-0-1-.... the bank count is synchronized between the controller and the sdram by resetting the bank count to zero. synchronization can occur upon issuing a reset command or at every exit from self refresh. bank addressing for the per-bank refresh count is the same as established for the single-bank precharge command. a bank must be idle before it can be refreshed. the controller must track the bank being refreshed by the per-bank refresh command. the refpb command must not be issued to the device until the following conditions are met: trfcab has been satisfied after the prior refab command trfcpb has been satisfied after the prior refpb command trp has been satisfied after the prior precharge command to that given bank trrd has been satisfied after the prior activate command (if applicable, for ex ample after activating a row in a dif- ferent bank than the one affected by the refpb command). the target bank is inaccessible during per-bank refresh cy cle time (trfcpb), however, other banks within the device are accessible and can be addressed during the cycle. duri ng the refpb operation, any of the banks other than the one being refreshed can be maintained in an active state or accessed by a read or a write command. when the per- bank refresh cycle has completed, the affected bank will be in the idle state. after issuing refpb, these conditions must be met: trfcpb must be satisfied before issuing a refab command trfcpb must be satisfied before issuing an activate command to the same bank trrd must be satisfied before issuing an activate command to a different bank trfcpb must be satisfied before issuing another refpb command an all-bank refresh command (refab) issues a refresh command to all banks. all banks must be idle when refab is issued (for instance, by issuing a precharge-all command prior to issuing an all-bank refresh command). refab also synchronizes the bank count between the controller and the sdram to zero. the refab command must not be issued to the device until the foll owing conditions have been met: trfcab has been satisfied after the prior refab command trfcpb has been satisfied after the prior refpb command trp has been satisfied after prior precharge commands when an all-bank refresh cycle has completed, all banks will be idle. after issuing refab: trfcab latency must be satisfied be fore issuing an activate command trfcab latency must be satisfied before issuing a refab or refpb command
rev 1.1 / oct. 2013 106 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) table. command scheduling se parations related to refresh lpddr3 devices provide significant fle xibility in scheduling refresh commands as long as the boundary conditions shown in figure ?tsrf definition? are met. in the most straightforward implementation s, a refresh command should be scheduled every trefi. in this case, self refresh can be entered at any time. users may choose to deviate from this regular refresh patter n, for example, to enable a period where no refreshes are required. in the extreme (e.g., lpddr3 4gb), the user can choose to issue a refresh burst of 8192 refresh com- mands at the maximum supported rate (limited by trefbw), followed by an extended period without issuing any refresh commands, until the refresh window is comple te. the maximum supported time without refresh com- mands is calculated as follows: trefw - (r/8) trefbw = trefw - r 4 trfcab. for example, a 4gb lpddr3 device at tc 85c can be operated without refresh co mmands up to 32ms - 8192 4 130ns 28 ms. both the regular and the burst/pause patt erns can satisfy refresh requirements if they are repeated in every 32ms win- dow. it is critical to satisfy the refresh requirement in ev ery rolling refresh window during refresh pattern transitions. the supported transition from a burst pattern to a regular di stributed pattern is shown in figure ?regular, distributed refresh pattern?. if this transition occurs immediately afte r the burst refresh phase, all rolling trefw intervals will meet the minimum required number of refreshes. a non-supported transition is shown in fi gure ?supported transition from repeti tive burst refresh?. in this example, the regular refresh pattern starts after the completion of the pause phase of th e burst/pause refresh pattern. for sev- eral rolling trefw intervals, the minimum nu mber of refresh commands is not satisfied. understanding this pattern transition is extremely important, even when only one pattern is employed. in self refresh mode, a regular distributed-refresh pattern must be assume d. it is recommend that self refresh mode is entered immediately following the burst phase of a burst/pause refresh pattern; upon exiting self refresh, begin with the burst phase (see figure ?recommended self-refresh entry and exit?). symbol minimum delay from to notes trfcab refab refab activate command to any bank refpb trfcpb refpb refab activate command to same bank as refpb refpb trrd refpb activate command to different bank than refpb activate refpb 1 activate command to different ba nk than prior activate command note: 1. a bank must be in the idle state before it is refreshed, so following an activate command refab is prohibited; refpb is sup- ported only if it affects a ba nk that is in the idle state.
rev 1.1 / oct. 2013 107 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note. 1. compared to repetitive burst refresh with subsequent refresh pause. 2. as an example, in a 4gb lpddr3 device at tc 85c, the distributed refresh pattern has one refresh command per 3.9 s; the burst refresh pattern has one refresh command per 0.52 s, followed by 28ms without any refresh command. figure. regular, distributed refresh pattern note. 1.shown with subsequent refresh pause to regular, distributed-refresh pattern. 2.as an example, in a 4g b lpddr3 device at tc 85c, the distributed refresh pattern has one refresh command per 3.9 s; the burst refresh pattern has one refresh command per 0.52 s, followed by 28ms without any refresh command. figure. supported transition from repetitive burst refresh 32 ms trefi trefi trefbw 64 ms trefbw 8,192 8,193 16,384 16,385 8,192 24,576 24,577 32,768 16,384 24,576 96 ms 0 ms 32 ms trefi trefi trefbw 64 ms trefbw 96 ms 0 ms 8,192 8,193 16,384 20,480 24,576 32,768
rev 1.1 / oct. 2013 108 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note. 1.shown with subsequent refresh pause to regular, distributed-refresh pattern. 2.there are only 4096 refresh commands in the indicated trefw window. this does not provide the minimum number of refresh commands (r). figure. nonsupported transition from repetitive burst refresh figure. recommended self-refresh entry and exit note. 1.in conjunction with a burst/pause refresh pattern. 32 ms trefi trefi trefbw 64 ms trefbw 96 ms 0 ms trefw = 32 ms not enough refresh commands in this refresh window 8,192 8,193 16,384 24,576 32,768 28,672 32 ms trefbw trefbw 8,192 8,193 16,384 0 ms self-refresh
rev 1.1 / oct. 2013 109 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) refresh requirements 1.minimum number of refresh commands lpddr3 requires a minimum number, r, of refresh (refab ) commands within any rolling refresh window (trefw = 32 ms @ mr4[2:0] = 011 or tc 85c). for trefw and trefi refresh multipli ers at different mr4 settings, refer to the mr4 definition. when using per-bank refresh, a refab command can be replaced by a full cycle of eight refpb commands. 2.burst refresh limitation to limit current consumption, a maximu m of 8 refab commands can be issued in any rolling trefbw (trefbw = 4 8 trfcab). this condition does not apply if refpb commands are used. 3.refresh requirements and self refresh if any time within a refresh window is spent in self refr esh mode, the number of required refresh commands in this particular window is reduced to: r* = r - ru{tsrf / trefi} = r - ru{r * tsrf / trefw}; where ru stands for the round-up function. notes: 1. a) time in self refresh mode is full y enclosed in the re fresh window (trefw). 2. b) at self refresh entry. 3. c) at self refresh exit. 4. d) several intervals in self refresh during one tr efw interval. in this example, tsrf = tsrf1 + tsrf2. figure. definition of tsrf cke enter self-refresh exit self-refresh tsrf trefw cke tsrf trefw exit self-refresh cke t srf trefw cke tsrf2 trefw tsrf1 enter self-refresh enter self-refresh exit self-refresh exit self-refresh tsrf = tsrf1 + tsrf2 a) b) c) d)
rev 1.1 / oct. 2013 110 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. all bank refresh operation note: 1. in the beginning of this example, the refpb bank is pointing to bank 0. 2. operations to other banks than the bank being refreshed are allowed during the t rfcpb period. figure. per bank refresh operation t0 t1 t2 t3 t4 tx ty ty+1 nop ck_t/ck_c ca0-9 [cmd] nop ab precharge >= t rpab any refab >= t rfcab refab >= t rfcab tx+1 nop nop t0 t1 tx tx+1 tx+2 ty tz nop ck_t/ck_c ca0-9 [cmd] nop ab precharge >= t rpab act refpb >= t rfcpb refpb >= t rfcpb refresh to bank 0 refresh to bank 1 tz+1 ty+1 nop nop activate command to bank 1 bank 1 row a row a
rev 1.1 / oct. 2013 111 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) self refresh operation the self refresh command can be used to retain data in the lpddr3 sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains da ta without external clocking. the device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by having cke low, cs_n low, ca0 low, ca1 low, and ca2 high at the rising edge of the clock. cke must be high during the previous clock cycle. cke must not go low while mrr, mrw, read, or write operat ions are in progress. to ensure that there is enough time to account for internal delay on the cke signal path, two nop commands are required after cke is driven low, this timing period is defined as tcpded. cke low will re sult in deactivation of input receivers after tcpded has expired. once the command is registered, cke must be held low to keep the device in self refresh mode. lpddr3 sdram devices can operate in self refresh in both the standard or elevated temperature ranges. lpddr3 devices will also manage self refresh power consumption when the operating temperature changes, lower at low tem- peratures and higher at high temperatures. once the sdram has entered self refresh mode, all of the ex ternal signals except cke, are ?don?t care?. for proper self refresh operation, power supply pins (vdd1, vdd2, and vddca) must be at valid levels. vddq may be turned off during self-refresh. prior to exiting self-refresh, vddq must be within specified limits. vrefdq and vrefca may be at any level within minimum and maximum le vels (see absolute maximum dc rati ngs). however prior to exiting self- refresh, vrefdq and vrefca must be within specified limi ts (see recommended dc operating conditions). the sdram initiates a minimum of one all-bank refresh command internally within tckesr period once it enters self refresh mode. the clock is internally disabled during self refresh operat ion to save power. the minimum time that the sdram must remain in self refresh mode is tckesr. the user may change the external clock frequency or halt the external clock one clock after self refresh entry is registered; however, th e clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock shall be stable and within specified limits for a minimum of 2 tck prior to the positive clock edge that registers cke high. once self refresh exit is registered, a delay of at least txsr must be satisfied befo re a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period txsr for proper opera- tion except for self refresh re-entry. nop commands must be registered on each positive clock edge during the self refresh exit interval txsr. the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from se lf refresh, it is required that at least one refresh command (8 per-bank or 1 all-bank) is issued before entry into a subsequent self refresh.
rev 1.1 / oct. 2013 112 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks of stable clock are prov ided and the clock frequency is between the minimum and ma ximum frequency for the particular spe ed grade. 2. device must be in the ?all banks idle? state prior to entering self refresh mode. 3. txsr begins at the rising edge of the clock after cke is driven high. 4. a valid command may be issued only after txsr is satisfied. nops shall be issued during txsr. figure. self refresh operation nop nop cke [cmd] 2 tck (min) cs_n enter valid enter self-refresh tckesr(min) exit self-refresh exit nop nop valid tiscke txsr(min) input clock frequency may be changed or stopped during self-refresh tihcke tihcke tiscke sr sr ck_t/ck_c tcpded
rev 1.1 / oct. 2013 113 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) partial array self refresh: bank masking lpddr3 sdram has 8 banks (additional banks may be requir ed for higher densities). each bank of lpddr3 sdram can be independently configured whether a self refresh operat ion is taking place. one mode register unit of 8 bits accessible via mrw command is assigned to program the bank masking status of each bank up to 8 banks. for bank masking bit assignments see mode register 16. the mask bit to the bank controls a refresh operation of enti re memory within the bank. if a bank is masked via mrw, a refresh operation to the entire bank is blocked and data re tention by a bank is not guar anteed in self refresh mode. to enable a refresh operation to a bank, a coupled mask bit has to be programmed, "unmasked". when a bank mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits, which is described in the following chapter. partial array self refresh: segment masking segment masking scheme may be used in lieu of or in combination with bank maskin g scheme in lpddr3 sdram. lpddr3 devices utilize 8 segments per bank. for segm ent masking bit assignments, see mode register 17. for those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is blocked when the mask bit to this segment is programmed, "masked". programming of segment mask bits is similar to the one of bank mask bits. with lpddr3, 8 segments are used as listed in mode register 17. one mode register unit is used for the programming of segment mask bits up to 8 bits. one more mode register unit may be reserved for future use. programming of bits in the reserved registers has no effect on the device operation. table: example of bank and segment masking use in lpddr3 devices note: 1. this table illustrates an example of an 8-bank lpddr3 device, when a refresh operation to bank 1 and bank 7, as well a s segment 2 and segment 7 are masked. segment mask (mr17) bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank mask (mr16) 01 0 0 0 0 01 segment 0 0 m m segment 1 0 m m segment 2 1 m m m m m m m m segment 3 0 m m segment 4 0 m m segment 5 0 m m segment 6 0 m m segment 7 1 m m m m m m m m
rev 1.1 / oct. 2013 114 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mode register read command the mrr command is used to read configuration and status data from sdram mode registers. the mrr command is initiated with cs_n low, ca0 low, ca1 low, ca2 low, and ca3 high at the rising edge of the clock. the mode reg- ister is selected by ca1f?ca0f and ca9r?ca4r. the mode register contents are available on the first data beat of dq[7:0] after rl tck + tdqsck + tdqsq following the risi ng edge of the clock where mrr is issued. subsequent data beats contain valid but undefined content, except in the case of the dq calibratio n function, where subsequent data beats contain valid content as described in the dq cali bration specification. all dqs are toggled for the duration of the mode register read burst. the mrr command has a burst length of eight. mrr operation (consisting of the mrr command and the correspond- ing data traffic) must not be interrupted. note: 1. mrrs to dq calibration registers mr32 and mr40 are described in dq calibration section. 2.only the nop command is supported during tmrr. 3.mode register data is valid only on dq[7:0] on the first be at. subsequent beats contain vali d but undefined data. dq[max:8] contain valid but undefined data for the duration of the mrr burst. 4.minimum mode register read to write latency is rl + ru(tdqsckmax/tck) + 8/2 + 1 - wl clock cycles. 5.minimum mode register read to mode register write latency is rl + ru(tdqsckmax/tck) + 8/2 + 1clock cycles. 6.in this example, rl = 8 for illustration purposes only. figure. mode register read timing after a prior read command, the mrr command must not be i ssued earlier than bl/2 clock cycles, or wl + 1 + bl/2 + ru(twtr/tck) clock cycles after a prior write command, as read bursts and write bursts must not be truncated by mrr. t0 t1 t2 t3 t4 t5 t6 t7 t8 ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c dq[0-7] reg a mrr rl=8 t mrr dout a reg a nop undef undef undef undef undef undef undef undef undef undef undef undef undef dq[8-max] t9 t10 t11 t12 t13 nop nop reg b reg b mrr nop nop nop dout b undef undef undef valid valid valid valid valid valid t mrr undef undef undef undef
rev 1.1 / oct. 2013 115 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1.only the nop command is supported during tmrr. 2.the minimum number of clock cycles from the burst read command to th e mrr command is bl/2. figure. read to mrr timing note: 1.the minimum number of clock cycles fr om the burst write command to the mrr command is [wl + 1 + bl/2 + ru(twtr/tck)]. 2. only the nop command is supported during tmrr. figure. burst write followed by mrr t0 t1 tx tx+1 tx+2 tx+3 tx+4 tx+5 ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c dq[0-7] col addr a read rl dout col addr a nop undef undef undef undef undef undef undef undef undef undef undef undef undef dq[8-max] tx+6 tx+7 tx+8 tx+9 tx+10 nop nop reg b reg b mrr nop nop nop undef undef valid t mrr bank m dout a0 a0 dout dout a0 a0 dout dout a0 a0 dout dout a0 a0 dout dout a0 a0 dout dout a0 a0 dout dout a0 a0 dout dout a0 a0 dout a0 t0 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 ck_t/ck_c ca0-9 [cmd] dqs_t/dqs_c col addr a write ba n col addr a din a0 din a2 din a3 din a1 valid wl tx+8 tx+9 din a4 din a6 din a7 din a5 reg b reg b mrr rl twtr tmrr
rev 1.1 / oct. 2013 116 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mrr following idle power-down state following the idle power-down state, an additional time, tm rri, is required prior to issuing the mode register read (mrr) command. this additional time (equ ivalent to trcd) is required in order to be able to maximize power-down current savings by allowing more power-up time for the mrr data path after exit from standby, idle power-down mode. note: 1. any valid command from the idle state except mrr. 2. tmrri = trcd. figure. mrr following power-down idle state cke [cmd] cs_n t0 tihcke ck_t/ck_c t2 ta+1 ta+2 tb tb+1 tb+2 ca[9:0] valid valid nop nop valid valid valid valid valid valid nop nop valid exit pd valid nop valid (except mrr) valid (except mrr) mrr nop valid tiscke txp(min) tmrr tmrri
rev 1.1 / oct. 2013 117 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) temperature sensor lpddr3 devices feature a temperature sensor whose status ca n be read from mr4. this sensor can be used to deter- mine an appropriate refresh rate, determine whether ac ti ming de-rating is required in the elevated temperature range, and/or monitor the operating temperature. either the temperature sensor or the device toper (see operating temperature range) may be used to determine whether operating temperature requirements are being met. lpddr3 devices shall monitor device temperature and update mr4 according to ttsi. upon exiting self-refresh or power-down, the device temperature status bits shall be no older than ttsi. when using the temperature sensor, the actual device case temperature may be higher than the toper specification (see operating temperature range) that applies for the st andard or elevated temperature ranges. for example, tcase may be above 85 ? c when mr4[2:0] equals 011b. lpddr3 devices shall allow for a 2 ? c temperature margin between the point at which the device temperature enters the elevated temperature range and point at which the con- troller re-configures the system accordingly. in the case of tight thermal coupling of the me mory device to external hot spots, the maximum device temperature might be higher than what is indicated by mr4. to assure proper operation using the temperature sensor , applications should consider the following factors: - tempgradient is the maximum temperature gradient experi enced by the memory device at the temperature of inter- est over a range of 2?c. - readinterval is the time period between mr4 reads from the system. - tempsensorinterval (ttsi) is maximum delay between internal updates of mr4. - sysrespdelay is the maximum time between a read of mr4 and the response by the system. in order to determine the required frequency of polling mr4, the system shall use the maximum tempgradient and the maximum response time of the syst em using the following equation: tempgradient x (readinterval + ttsi + sysrespdelay) ? 2 o c for example, if tempgradient is 10 o c/s and the sysrespdelay is 1ms: 10 o c/s x (readinterval + 32ms + 1ms) <= 2 o c in this case, readinterval shall be no greater than 167ms. paramter sysmbol min/max value unit note system temperature gradient tempgradient max system dependent o c/s mr4 read interval readinterval max system dependent ms temperature sensor interval ttsi max 32 ms system response delay sysrespdelay max system dependent ms mr4 temp margin tempmargin max 2 o c
rev 1.1 / oct. 2013 118 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. temp sensor timing temp 2 o c ttsi readinterval < (ttsi + readinterval + sysrespdelay) sysrespdelay mr4 = 0x03 mr4 = 0x86 mr4 = 0x86 mr4 = 0x86 mr4 = 0x86 mr4 = 0x06 mrr mr4 = 0x03 mrr mr4 = 0x86 device time t e m p g r a d i e n t mr4 temperature sensor update host mr4 read temp margin trip level
rev 1.1 / oct. 2013 119 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) dq calibration lpddr3 device features a dq calibration function that ou tputs one of two predefined system timng calibration pat- terns. a mode register read to mr32 (pattern ?a?) or mr40 (pattern ?b?) will return the specified pattern on dq[0] and dq[8] for x16 devices, and dq[0], dq[8], dq[16], an d dq[24] for x32 devices. for x16 devices, dq[7:1] and dq[15:9] may optionally drive the same information as dq[0] or may drive 0b during the mrr burst. for x32 devices, dq[7:1], dq[15:9], dq[23:17],and dq[31: 25] may optionally drive the same information as dq[0] or may drive 0b during the mrr burst. table. data calibration pattern description figure. mr32 and mr40 dq calibration timing example note: 1. mode register read has a burst length of eight. 2. mode register read operat ion shall not be interrupted. 3. mode register reads to mr32 and mr40 driv e valid data on dq[0] during the entire burst. for x16 devices, dq[8] shall drive t he same information as dq[0] during the burst. for x32 devices, dq[8], dq[16] and dq[24] shall drive the same information as dq[0] during the burst. 4. for x16 devices, dq[7:1] and dq[15:9] may optionally drive the same information as dq[0] or they may drive 0b during the bur st. for x32 devices, dq[7:1], dq[15:9], dq[23:17] and dq[31:25] may optionally drive the same information as dq[0] or they may drive 0b during the burst. bit time 0 bit time 1 bit time 2 bit time 3 bit time 4 bit time 5 bit time 6 bit time 7 pattern a (mr32) 101 0 101 0 pattern b (mr40)00110011 ca0-9 dq[0] ck_t / ck_c rl = 6 dqs_t t0 t2 t1 t3 t4 t5 t6 t7 t8 [cmd] t mrr = 4 dq[7:1] t mrr = 4 cmd not allowed mrr32 reg 32 reg 32 dqs_c optionally driven the same as dq0 or 0b dq[8] dq[15:9] dq[16] dq[23:17] dq[24] dq[31:25] x16 x32 pattern ?a? pattern ?b? t9 t10 t11 t12 t13 t14 undef undef undef undef undef undef 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 undef undef undef undef undef undef 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 undef undef undef undef undef undef 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 undef undef undef undef undef undef 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 undef undef undef 0 0 1 1 0 0 1 1 undef undef undef 0 0 1 1 0 0 1 1 undef undef undef 0 0 1 1 0 0 1 1 undef undef undef 0 0 1 1 0 0 1 1 undef undef undef 1 0 1 0 1 0 1 0 undef undef undef 1 0 1 0 1 0 1 0 undef undef undef 1 0 1 0 1 0 1 0 undef undef undef 1 0 1 0 1 0 1 0 mrr40 reg 40 reg 40
rev 1.1 / oct. 2013 120 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mode register write command the mrw command is used to write configuration data to mode registers. the mrw command is initiated with cs_n low, ca0 low, ca1 low, ca2 low, and ca3 low at the rising edge of the clock. the mode register is selected by ca1f-ca0f, ca9r-ca4r. the data to be written to the mo de register is contained in ca9f-ca2f. the mrw command period is defined by tmrw. mode register writes to read-o nly registers have no impact on the functionality of the device. note: 1. at time ty, the device is in the idle state. 2. only the nop command is supported during tmrw. figure. mode register write timing example mode register write mrw can only be issued when all banks ar e in the idle precharge state. one meth od of ensuring that the banks are in this state is to issue a precharge-all command. mrw reset the mrw reset command brings the device to the device auto-initialization (res etting) state in the power-on initial- ization sequence. the mrw reset command can be issued from the idle state. this command resets all mode regis- ters to their default values. after mrw reset, boot timings mu st be observed until the device initialization sequence is complete and the device is in the idle state. ar ray data is undefined after the mrw reset command. if the initialization is to be performed at-speed (greater than the recommended boot clock frequency), then ca train- ing may be necessary to ensure setup and hold timings. since the mrw reset command is required prior to ca train- ing an alternate mrw reset command with an op-code of 0xfch should be used. this encoding ensures that no transitions occur on the ca bus. prior to ca training, it is recommended to hold the ca bus stable for one cycle prior to, and one cycle after, the issuance of the mrw reset co mmand to ensure setup and hold timings on the ca bus. t0 t1 t2 tx tx+1 tx+2 ty ty+1 ty+2 ck_t/ck_c mr addr ca0-9 mr data [cmd] mrw valid t mrw cmd not allowed t mrd mr addr mr data mrw
rev 1.1 / oct. 2013 121 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. optional mrw reset command and optional cs_n assertion are allowed, when optional mrw reset command is used, tinit4 starts at td?. figure. mode register write timing for mrw reset current state command intermediate state next state all banks idle mrr mode register reading (all banks idle) all banks idle mrw mode register writing (all banks idle) all banks idle mrw (reset) resetting (device auto-init) all banks idle bank(s) active mrr mode register reading (bank(s) active) bank(s) active mrw not allowed not allowed mrw (reset) not allowed not allowed [cmd] ck_t / ck_c fch cs_n fch mrw (optional) mrw cke td td? te fch fch regb regb mrr ca0-9 tinit3 cmd not allowed optional
rev 1.1 / oct. 2013 122 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mode register write zq calibration command the mrw command is used to initiate the zq calibration command. this command is used to calibrate the output driver impedance across process, temperature, an d voltage. lpddr3 devices support zq calibration. there are four zq calibration commands and related timing s: tzqinit, tzqreset, tzqcl, and tzqcs. tzqinit is for initialization calibration; tzqreset is fo r resetting zq to the default output impe dance; tzqcl is for long calibration(s); and tzqcs is for short calibration(s). the initialization zq calibration (zqinit) must be perfor med for lpddr3. zqinit provides an output impedance accu- racy of 15 percent. after initialization, the zq calibration long (zqcl) can be used to recalibrate the system to an output impedance accuracy of 15 percent. a zq calibration short (zqcs) can be used peri odically to compensate for temperature and voltage drift in the system. the zq reset command (zqreset) resets the output impedance calibration to a default accuracy of 30% across pro- cess, voltage, and temperature. this command is used to ensure output impedance accuracy to 30% when zqcs and zqcl commands are not used. one zqcs command can effectively correct at least 1.5% (zq correction) of output impedance errors within tzqcs for all speed bins, assuming the maximum sensitivities specif ied are met. the appropriate interval between zqcs com- mands can be determined from using thes e tables and system-specific parameters. lpddr3 devices are subject to temperature drift rate (tdriftr atee) and voltage drift rate (v driftrate) in various applica- tions. to accommodate drift rates and calculate the necessary interval between zqcs commands, apply the following formula: where tsens = max(drondt) and vsens = max(drondv) define the lpddr3 temperature and voltage sensitivities. for example, if tsens = 0.75% / ? c, vsens = 0.20% / mv, tdriftrate = 1 ? c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: a zq calibration command can only be issu ed when the device is in the idle st ate with all banks precharged. odt shall be disabled via the mode register or th e odt pin prior to issuing a zq calibrat ion command. no other activities can be performed on the data bus and the data bus shall be un-te rminated during calibration periods (tzqinit, tzqcl, or tzqcs). the quiet time on the da ta bus helps to accurately calibrate output impedance. there is no required quiet time after the zq reset command. if multiple devices share a single zq resistor, only one device can be calibrating at any given time. after calibration is complete, the zq ball circui try is disabled to reduce power consumption. in systems sharing a zq resistor between devices, the controller mu st prevent tzqinit, tzqcs, and tzqcl overlap between the devices. zq reset overlap is acceptable. zqcorrection tsens tdriftrate ? ?? vsens vdriftrate ? ?? + ------------------------------------------------------------------------------------------------------------------------------- --- 1.5 0.75 1 ? ?? 0.20 15 ? ?? + --------------------------------------------------------------- - 0.4 s =
rev 1.1 / oct. 2013 123 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. only the nop command is su pported during zq calibration. 2. cke must be registered high continuously during the calibration period. 3. all devices connected to the dq bus should be high-z during the calibration process figure. zq calibration initialization timing note: 1. only the nop command is su pported during zq calibration. 2.cke must be registered high contin uously during the calibration period. 3.all devices connected to the dq bus should be high-z duri ng the calibration process. figure. zq calibration short timing note: 1. only the nop command is su pported during zq calibration. 2. cke must be registered high continuously during the calibration period. 3. all devices connected to the dq bus should be high-z during the calibration process. figure. zq calibration long timing ca0-9 ck_t / ck_c t0 t2 t1 t3 t4 t5 tx tx + 1 tx + 2 [cmd] cmd not allowed t zqinit mrw mr addr mr data any ca0-9 ck_t / ck_c t0 t2 t1 t3 t4 t5 tx tx + 1 tx + 2 [cmd] cmd not allowed t zqcs mrw mr addr mr data any ca0-9 ck_t / ck_c t0 t2 t1 t3 t4 t5 tx tx + 1 tx + 2 [cmd] cmd not allowed t zqcl mrw mr addr mr data any
rev 1.1 / oct. 2013 124 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. only the nop command is su pported during zq calibration. 2. cke must be registered high continuously during the calibration period. 3. all devices connected to the dq bus should be high-z during the calibration process. figure. zq calibration reset timing example zq external resistor value, tolerance and capacitive loading to use the zq calibration function, an rzq 1% tolerance external resistor must be connected between the zq pin and ground. a single resistor can be used for each device or one resistor can be shared between multiple devices if the zq calibration timings for each device do not overlap. the total capacitive loading on th e zq pin must be limited (see pin capacitance table). ca0-9 ck_t / ck_c t0 t2 t1 t3 t4 t5 tx tx + 1 tx + 2 [cmd] cmd not allowed t zqreset mrw mr addr mr data any
rev 1.1 / oct. 2013 125 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mode register write - ca training mode because ca inputs are double data rate, it may be diffic ult for memory controller to satisfy ca input setup/hold timings at higher frequency. ca training mechanism is provided. ca training sequence a) ca training mode entry: mode register write to mr#41 b) ca training session calibrate ca0, ca1, ca2, ca3, ca5, ca6, ca7 and ca8 (see the table ?c a to dq mapping (... #mr41)?) c) ca to dq mapping change: mode register write to mr#48 d) additional ca training session calibrate remaining ca pins (ca4 an d ca9) (see the table ?ca to dq mapping (... #mr48)?) e) ca training mode exit: mode register write to mr#42 note: 1. unused dq must be valid high or low during data output period. unused dq may transition at the same time as the active dq. dqs must remain static and not transition. 2. ca to dq mapping change via mr #48 omitted here for clarity of the timing diagram. both mr41 and mr48 training sequences mus t be completed before exiting the training mo de (mr42). to enable a ca to dq mapping change, cke must be driven high prior to issuance of the mrw 48 command. for details, pl ease refer to ca training sequence section. 3. because data out control is asynchronous and will be an analog delay fr om when all the ca data is available, tadr and tmrz a re defined from ck_t falling edge. 4. it is recommended to hold the ca bus stable for one cycle prior to and one cycle after the issuance of the mrw ca training e ntry command to ensure setup and hold timings on the ca bus. 5. optional mrw 41, 48, 42 command and ca calibr ation command are allowed. to complement these optional commands, optional cs_n assertions are also a llowed. all timing must comp rehend these optional cs_n assertions: a) tadr starts at the falli ng clock edge after the last registered cs_n assertion. b) tcacd, tcackel, tcamrd start with the rising clock edge of the last cs_n assertion. c) tcaent, tcaext need to be met by the first cs_n assertion. d) tmrz will be met after the falling clock edge following the first cs_n assertion with exit (mr42) command. ca0-9 ck_t / ck_c even tcackel mr41,48 (ca cal. entry) cax r r# mr42 (ca cal. exit) csb cax r r# tcaent tcacd tcamrd dqs tadr tadr tcackeh tcaext cax r cay r odd dqs cax r cay r tmrz don?t care cay cax mr42 (optional) mr41,48 (optional) mr41,48 (optional) mr42 (optional) cax r r# cay cax r r# cax optional optional
rev 1.1 / oct. 2013 126 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) the lpddr3 sdram may not properly recognize mode register write command at normal operation freq uency before ca training is finished. special encodings are provided for ca training mode enable/disable. mr#41 and mr#42 encodings are selected so th at rising edge and falling edge values ar e the same. the lpddr3 sdram will recogniz e mr#41 and mr#42 at normal operation frequency ev en before ca timing adjustment is finished. calibration data will be output through dq pins. ca to dq maping is described in the table below. after timing calibration with mr#41 is finished, users will issue mrw to mr#48 and calibrate remaining ca pins (ca4 and ca9) using dq0,1,8,9 as calibration data output pins in the table below. table. ca training mode enable ( mr#4 1(29h, 0010 1001b), op=a4h(1010 0100b)) table. ca training mode disable (mr#42(2ah, 0010 1010b), op=a8h(1010 1000b)) table. ca to dq mapping (ca tr aining mode enabled with mr#41) table. ca training mode enable (mr#48(30h, 0011 0000b), op=c0h(1100 0000b)) table. ca to dq mapping (ca tr aining mode enabled with mr#48) note: other dqs must have valid output (either high or low) ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 rising edge llllhllhlh falling edge l l l l h l l h l h ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 rising edge lllllhlhlh falling edge lllllhlhlh ca0 ca1 ca2 ca3 ca5 ca6 ca7 ca8 clock edge dq0 dq2 dq4 dq6 dq8 dq10 dq12 dq14 ck_t rising edge dq1 dq3 dq5 dq7 dq9 dq11 dq13 dq15 ck_t falling edge ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 rising edge llllllllhh falling edge llllllllhh ca4 ca9 clock edge dq0 dq8 ck_t rising edge dq1 dq9 ck_t falling edge
rev 1.1 / oct. 2013 127 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) mode register write - wr leveling mode in order to provide for improved signal integrity performance, the lpddr3 sdram provides a write leveling feature to compensate for timing skew, affecting timing parameters such as tdqss, tdss, and tdsh. the memory controller uses the write leveling feature to re ceive feedback from the sdram allowing it to adjust the clock to data strobe signal relationship for each dqs_t/dqs_c signal pair. the me mory controller performing the leveling must have adjustable delay sett ing on dqs_t/dqs_c signal pair to align the ri sing edge of dqs signals with that of the clock signal at the dram pin. the dram asynchronously feeds back clk, sampled with the rising edge of dqs signals. the controller repeatedly delays dqs signals until a transition from 0 to 1 is detected. the dqs signals delay established through this exercise ensures the tdqss specification can be met. all dqs signals may have to be leveled independantly. duri ng write leveling operations each dqs signal latches the clock with a rising strobe edge and drives th e result on all dq[n] of its respective byte. the lpddr3 sdram enters into write leveli ng mode when mode register mr2[7] is set high. when entering write lev- eling mode, the state of the dq pins is undefined. during write leveling mode , only nop commands are allowed, or mrw command to exit write leveling operation. upon completi on of the write leveling operation, the dram exits from write leveling mode when mr2[7] is reset low. the controller will drive dqs_t low and dqs_c high after a delay of twldqsen. after time twlmrd, the controller provides dqs signal input which is used by the dram to sa mple the clock signal driven from the controller. the delay time twlmrd(max) is controller dependent. the dram samp les the clock input with the rising edge of dqs and pro- vides asynchronous feedback on all the dq bits after time twlo. the controller samples this information and either increment or decrement the dqs_t and/or dqs_c delay settin gs and launches the next dqs/dqs# pulse. the sample time and trigger time is controller dependent. once the fo llowing dqs_t/dqs_c transition is sampled, the controller locks the strobe delay settings, and write leveling is achieved for the device. the figure below describes the timing for the write leveling operation. figure. write leveling timing diagram ca0-9 ck_t / ck_c dqs_t [cmd] twldqsen mrw ca ca dqs_c nop mrw ca ca nop nop nop nop nop nop nop nop nop nop nop valid twlmrd twlo tdqsh tdqsl twlo tmrd dqs twlh twls twlh twls
rev 1.1 / oct. 2013 128 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) on die termination (odt) odt funtional description odt (on-die termination) is a feature of the lpddr3 sdram th at allows the dram to turn on/off termination resistance for each dq, dqs_t, dqs_c and dm via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. unlike other command inputs, the odt pin directly controls od t operation and is not sampled by the clock. the odt feature is turned off and not supported in self-refresh and deep power down modes. odt operation can optionally be enabled during cke power down via a mode re gister. note that if odt is enabled during power down mode vddq may not be turned off during power down. the dram will also disabl e termination during read operations. a simple functional representation of th e dram odt feature is shown in the figure "functional representation of odt". figure. functinoal representation of odt the switch is enabled by the internal odt control logic, whic h uses the external odt pin and other mode register control information. the value of rtt is determined by the settings of mode register bits. the odt pin will be ignored if the mode register mr11 is programmed to disable odt, in self -refresh, in deep power down, in cke power down (mode register option) and during read operations. odt mode registor the odt mode is enabled if mr11 op<1:0> are non zero. in th is case, the value of rtt is determined by the settings of those bits. the odt mode is disabled if mr11 op<1:0> are zero. mr11 op<2> determines whether odt, if enabled through mr11 op<1:0>, will operate during cke power down. asynchronous odt the odt feature is controlled asynchronously based on the status of the odt pin, except odt is off when:. - odt is disabled through mr11 op<1:0> - dram is performing a read operation (rd or mrr) - dram is in cke power down and mr11 op<2> is zero - dram is in self-refresh or deep power down modes - dram is in ca training mode in asynchronous odt mode, the following timing para meters apply when odt op eration is controlled by the odt pin: todton,min,max, todtoff,min,max. minimum rtt turn-on time (todtonmin) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on . maximum rtt turn on time (todtonmax) is the point in time when the odt resistance is fully on. todt onmin and todtonmax are measured from odt pin high. minimum rtt turn-off time (todtoffmin) is the point in ti me when the device terminat ion circuit starts to turn off the odt resistance. maximum odt turn off time (todtoffmax) is the point in time when the on-die termination has reached high impedance. todtoffmin and todtoffmax are measured from odt pin low. dq, dqs, dm to other circuitry like rcv, ... rtt vddq switch odt
rev 1.1 / oct. 2013 129 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) odt during read operations (rd or mrr) during read operations, lpddr3 sdram will disable termin ation and disable odt control through the odt pin. after read operations are completed, odt control is resu med through the odt pin (if odt mode is enabled). odt during power down when mr11 op<2> is zero, termination control through the od t pin will be disabled when the dram enters cke power down. after a power down command is registered, termination will be disabled within a ti me window specified by tod- td,min,max. after a power down exit command is registered, termination will be enabled within a time window specified by todte,min,max. minimum rtt disable time (todtd,min) is the point in time when the device termination circuit will no longer controlled by the odt pin. maximum odt disable time (todtd,max) is th e point in time when the on-d ie termination will be in high impedance. minimum rtt enable time (todte,m in) is the point in time when the device term ination circuit will no longer be in high impedance. the odt pin shall control the device terminatio n circuit after maximum odt enable time (todte,max) is satisfied. when mr11 op<2> is enabled and mr11 op<1:0> are non ze ro, odt operation is supported during cke power down with odt control through the odt pin. odt during self refresh lpddr3 sdram disables the odt function during self refresh. after a self refresh command is registered, termination will be disabled within a time window specified by todtd,min,max. after a self refresh exit command is registered, ter- mination will be enabled within a ti me window specified by todte,min,max. odt during deep power down lpddr3 sdram disables the odt function during deep powe r down. after a deep power down command is registered, termination will be disabled. odt during ca training and write leveling during ca training mode, lpddr3 sdram will disable on-die termination and ignore the state of the odt control pin. for odt operation during write leveling mode, refer to the dram termination function in write leveling mode table for termination activation and deac tivation for dq and dqs_t/dqs_c. table. dram termination function in write leveling mode if odt is enabled, the odt pin must be high, in writ e leveling mode. table. odt states truth table note: 1. odt is enabled with mr11[1:0]=01b, 10b or 11b and odt pin high. odt is disabled with mr11[1:0]=00b or odt pin low. odt pin dqs_t/dqs_c termination dq termination de-asserted off off asserted on off write read/dq cal zq cal ca training write leveling dq termination enabled disabled disabled disabled disabled dqs termination enabled disabled disabled disabled enabled
rev 1.1 / oct. 2013 130 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. asynchronous odt timing example for rl=12 figure. automatic odt timing during read operation example for rl=m note: 1. the automatic rtt turn-off delay, taodtoff, is referenced from the rising edge of "rl-2" clock at tm-2. 2. the automatic rtt turn-on delay, taodton, is referenced from the rising edge of "rl+ bl/2" clock at tm+4. figure. odt timing during power down, self re fresh, deep power down entry/exit example note: 1. upon exit of deep power down mode, a complete power-up initialization sequence is required. ca0-9 dqs ck_t / ck_c dqs_t t0 t10 t9 t11t12t13t14t15t16 [cmd] read col addr col addr dqs_c t17 t18 t19 bank n din a0 din a2 din a3 din a1 din a4 din a6 din a7 din a5 todtoff(min) todtoff t20 t21 tdqsck rl=12 todtoff(max) odt on odt off todton(min) todtoon(max) odt dram_rtt ca0-9 dqs ck_t / ck_c dqs_t t0 tm-3 t1 tm-2 tm-1 tm tm+1 tm+2 tm+3 [cmd] read col addr col addr dqs_c tm+4 tm+5 tm+6 bank n din a0 din a2 din a3 din a1 din a4 din a6 din a7 din a5 taodtoff tm+7 tm+8 tdqsck rl=12 odt on odt off taodton bl/2 thz(dqs) odt on odt dram_rtt tlz(dqs) dram_rtt ck_t / ck_c t0 t2 t1 t3 tm-2 tm-1 tm tm+1 tm+2 tn todtd odt on odt off cke odt odt on todte
rev 1.1 / oct. 2013 131 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) power-down power-down is entered synchronously when cke is registered low and cs_n is high at the rising edge of clock. cke must not go low while mrr, mrw, read, or write operat ions are in progress. cke can go low while any other operations such as row activation, precharge, auto precha rge, or refresh are in prog ress, but the power-down idd specification will not be applied until such operations are complete. power-down entry and exit are shown in following figures. entering power-down deactivates the input and output buffers, excluding cke. to ensure that there is enough time to account for internal delay on the cke si gnal path, two nop commands are required after cke is driven low, this tim- ing period is defined as tcpded. cke low will result in de activation of input receivers after tcpded has expired. in power-down mode, cke must be held low; all other input si gnals are ?don?t care.? cke low must be maintained until tcke,min is satisfied. vrefca must be main tained at a valid level during power-down. vddq can be turned off during power-down. if vddq is turned off, vrefdq must also be turned off. prior to exiting power-down, both vddq and vrefdq must be within their respective minimum/maximum operating ranges. no refresh operations are performed in power-down mode. the maximum duration in powe r-down mode is only lim- ited by the refresh requirements outl ined in the refresh command section. the power-down state is exited when cke is registered hi gh. the controller must driv e cs_n high in conjunction with cke high when exiting the power-down state. cke high must be maintained until tcke is satisfied. a valid, exe- cutable command can be applied with power-down exit late ncy txp after cke goes high. power-down exit latency is defined in the ac timing parameter table. if power-down occurs when all banks are idle, this mode is referred to as idle power- down; if power-down occurs when there is a row active in any bank, this mode is refe rred to as active power-down. for the description of odt operation and specifications during power-down entry and exit, see sectio n "on-die termination". note: 1. input clock frequency can be changed or the input clock stopped during power-down , provided that the clock frequency is between the minimum and maximum specified fr equencies for the speed grade in use, and that prior to power-down exit, a minimum of 2 stable clocks complete. figure. basic power down entry and exit timing diagram ck_t/ck_c cke [cmd] tinit2 = 2 tck (min) cs_n enter nop valid enter power-down mode tcke(min) exit power-down mode exit nop valid valid tiscke txp(min) input clock frequency may be changed or stopped during power-down tihcke tihcke tiscke pd pd tcke(min) nop tcpded
rev 1.1 / oct. 2013 132 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) figure. cke intensive environment note: 1. the pattern shown can repeat over an extended period of time . with this pattern, all ac and dc timing and voltage specificat ions with temperature and voltage drift are ensured. figure. refresh to refresh timing with cke intensive environment note: 1. cke must be held high until the end of the burst operation. 2. cke can be registered low at rl + ru(tdqsck(max)/tck) + bl /2 + 1 clock cycles after the clock on which the read command is registered. figure. read to power-down entry ck_t/ck_c cke t cke t cke t cke t cke ck_t/ck_c cke t cke t cke t cke t cke ref ref t refi t xp t xp [cmd] ck_t/ck_c cke [cmd] t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 rd rl dq dqs_t/dqs_c t iscke q q q q q q q q
rev 1.1 / oct. 2013 133 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. cke must be held high until the end of the burst operation. 2. cke can be registered low at rl + ru(tdqsck/tck)+ bl/2 + 1 clock cycles after the clock on which the read command is regis- tered. 3. bl/2 with trtp = 7.5ns and tras (min) is satisfied. 4. start internal precharge. figure. read with auto prec harge to power-down entry note: 1. cke can be registered low at wl + 1 + bl/2 + ru(twr/tck) clock cycles after the clock on which the write command is regis- tered. figure. write to power-down entry ck_t/ck_c cke [cmd] t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 rda rl dq dqs_t/dqs_c pre bl/2 t iscke q q q q q q q q ck_t/ck_c cke cmd t0 t1 tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 tx+3 tx+4 wr d d d d wl dq dqs_t/dqs_c t iscke bl=8 twr tm d d d d bl/2
rev 1.1 / oct. 2013 134 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note: 1. cke can be registered low at wl + 1 + bl/2 + ru(twr/t ck) + 1 clock cycles after the write command is registered. 2. start internal precharge. figure. write with auto precharge to power-down entry note. 1. cke may go low tihcke af ter the clock on which the refresh command is registered. figure. refresh command to power-down entry note. 1. cke may go low tihcke after the clock on which the activate command is registered. figure. activate command to power-down entry ck_t/ck_c cke cmd t0 t1 tm tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 tx+3 tx+4 wra d d d d wl dq dqs_t/dqs_c bl=8 pre t iscke d d d d t wr ck_t/ck_c cke cmd ref t iscke t ihcke t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 cke cmd act t iscke t ihcke t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck_t/ck_c
rev 1.1 / oct. 2013 135 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) note. 1. cke can go low tihcke after the clock on which the precharge command is registered. figure. precharge command to power-down entry note. 1. cke can be registered low rl + ru (tdqsck/tck)+ bl/2 + 1 clock cycles after the clock on which the mrr command is reg- istered. 2. cke should be held high until the end of the burst operation. figure. mrr to power-down entry note. 1. cke may be registered low tmrw after the clock on which the mode register write command is registered. figure. mrw command to power-down entry cke cmd pre t iscke t ihcke t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck_t/ck_c ck_t/ck_c cke [cmd] t0 t1 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 tx+8 tx+9 mrr q rl dq dqs_t/dqs_c t iscke q q q q q q q cke cmd mrw t iscke t mrw t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
rev 1.1 / oct. 2013 136 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) deep power down deep power-down is entered when cke is registered low with cs_n low, ca0 high, ca1 high, and ca2 low at the rising edge of clock. a nop command must be driven in the clock cycle following the power-down command. cke is not allowed to go low while mode register, read, or write operations are in progress. all banks must be in idle state with no activity on the da ta bus prior to entering the deep power down mode. during deep power-down, cke must be held low. in deep power-down mode, all input buffers except cke, al l output buffers, and the power supply to internal circuitry may be disabled within the sdram. all power supplies must be within specified limits prior to exiting deep power- down. vrefdq and vrefca may be at any level within mi nimum and maximum levels (see abolute maximum ratings). however prior to exiting deep power-down, vref must be within specified limits (see recommended dc operating conditions). the contents of the sdram will be lost upon entry into deep power-down mode. the deep power-down state is exited when cke is register ed high, while meeting tiscke with a stable clock input. the sdram must be fully re-initialized as described in th e power up initialization sequence. the sdram is ready for normal operation after the initialization sequence. the sdram is ready for normal operation after the initialization sequence is completed. for the description of odt operatio n and specifications during dp d entry and exit, see section on-die termination. note: 1. initialization sequence ma y start at any time after tc. 2. tinit3, and tc refer to timings in the lpddr3 initializati on sequence. for more detail, see power-up and initialization. 3. input clock frequency may be changed or the input clock stopped during deep powe r-down, provided that upon exiting deep power-down, the clock is stable and within specified limits for a minimum of 2 clock cy cles prior to deep power-down exit and t he clock frequency is between the minimum and maxi mum frequency for the particular speed grade. figure. deep power down entry and exit timing diagram cke [cmd] tinit2 = 2 tck (min) cs_n exit nop nop enter deep power-down mode tdpd exit deep power-down mode tiscke input clock frequency may be changed or the input clock stopped during deep power-down tihcke tiscke dpd reset tinit3 = 200 us (min) nop enter dpd ck_t/ck_c tc trp nop tcpded
rev 1.1 / oct. 2013 137 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) input clock stop and frequency change lpddr3 devices support input clock frequency change during cke low under the following conditions: ? tck(abs)min is met for each clock cycle; ? refresh requirements apply during clock frequency change; ? during clock frequency change, only refab or refpb commands may be executing; ? any activate or precharge commands have executed to completion prior to changing the frequency; ? the related timing conditions (trcd, trp) ha ve been met prior to changing the frequency; ? the initial clock frequency shall be maintained fo r a minimum of 3 clock cycles after cke goes low; ? the clock satisfies tch(abs) and tcl(abs) for a mi nimum of 2 clock cycles prior to cke going high. after the input clock frequency is chan ged and cke is held high, additional mrw commands may be required to set the wr, rl etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock fre- quency. lpddr3 devices support clock stop during cke low under the following conditions: ? ck_t is held low and ck_c is held high during clock stop; ? refresh requirements ap ply during clock stop; ? during clock stop, only refab or refpb commands may be executing; ? any activate or precharge commands have execut ed to completion prior to stopping the clock; ? the related timing conditions (trcd, trp) have been met prior to stopping the clock; ? the initial clock frequency shall be maintained fo r a minimum of 3 clock cycles after cke goes low; ? the clock satisfies tch(abs) and tcl(abs) for a mi nimum of 2 clock cycles prior to cke going high. lpddr3 devices support input clock frequency change during cke high under the following conditions: ? tck(abs)min is met for each clock cycle; ? refresh requirements apply during clock frequency change; ? any activate, read, write, precharge, mode regi ster write, or mode register read commands must have executed to completion, including any associat ed data bursts prior to changing the frequency; ? the related timing conditions (trcd, twr, trp, tmrw, tm rr, etc.) have been met prior to changing the frequency; ? cs_n shall be held high during clock frequency change; ? during clock frequency change, only refab or refpb commands may be executing; ? the lpddr3 device is ready for normal operation after th e clock satisfies tch(abs) an d tcl(abs) for a minimum of 2tck + txp. after the input clock frequency is change d, additional mrw commands may be re quired to set the wr, rl etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. lpddr3 devices support clock stop during cke high under the following conditions: ? ck_t is held low and ck_c is held high during clock stop; ? cs_n shall be held high during clock stop; ? refresh requirements ap ply during clock stop; ? during clock stop, only refab or refpb commands may be executing; ? any activate, read, write, precharge, mode register writ e, or mode register read commands must have executed to completion, including any associated da ta bursts prior to stopping the clock; ? the related timing conditions (trcd, twr, trp, tmrw, tmrr, etc.) have been met prior to stopping the clock; ? the lpddr3 device is ready for normal operation after the clock is restarted and satisfies tch(abs) and tcl(abs) for a minimum of 2tck + txp.
rev 1.1 / oct. 2013 138 h9cknnn8gtmplr lpddr3-s8b 8gb(x32) no operation command the purpose of the no operation command (nop) is to pr event the lpddr3 device from registering any unwanted command between operations. only when the cke level is constant for clock cycle n-1 and clock cycle n, a nop command may be issued at clock cycle n. a nop command has two possible encodings: 1. cs_n high at the clock rising edge n. 2. cs_n low and ca0, ca1, ca2 hi gh at the clock rising edge n. the no operation command will not terminat e a previous operation that is still exec uting, such as a burst read or write cycle.

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